Masami Usami

According to our database1, Masami Usami authored at least 6 papers between 1994 and 2000.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2000
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz.
IEEE J. Solid State Circuits, 2000

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM.
IEEE J. Solid State Circuits, 2000

1998
A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM.
IEEE J. Solid State Circuits, 1998

1996
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry.
IEEE J. Solid State Circuits, 1996

1995
A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM.
IEEE J. Solid State Circuits, April, 1995

1994
A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates.
IEEE J. Solid State Circuits, April, 1994


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