Kenichi Ohhata

According to our database1, Kenichi Ohhata authored at least 16 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC.
IEEE J. Solid State Circuits, 2019

2018
A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A 2.3-MW, 950-MHz, 8-Bit Fully-Time-Based Subranging ADC Using Highly-Linear Dynamic VTC.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Low-Power, High-Speed Time-Based Subranging ADCs.
Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018

2014
1-GHz, 17.5-mW, 8-bit Subranging ADC Using Offset-Cancelling Charge-Steering Amplifier.
IEICE Trans. Electron., 2014

Automatic technique of distortion compensation in resistor ladder for high-speed and low-power ADC.
IEICE Electron. Express, 2014

Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimization.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2011
A 25 Gb/s 65-nm CMOS Low-Power Laser Diode Driver With Mutually Coupled Peaking Inductors for Optical Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Low-Offset, Low-Power Latched Comparator Using Capacitive Averaging Technique.
IEICE Trans. Electron., 2011

2010
17 Gb/s VCSEL driver using double-pulse asymmetric emphasis technique in 90-nm CMOS for optical interconnection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 25Gb/s laser diode driver with mutually coupled peaking inductors for optical interconnects.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture.
IEEE J. Solid State Circuits, 2009

2008
Sandwich Structure Type RF-MEMS Variable Capacitor with Low Voltage Controllability and Wide Tuning Range.
IEICE Trans. Commun., 2008

Feedthrough reduction technique for track-and-hold circuit with body-bias control circuit.
IEICE Electron. Express, 2008

2007
A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit.
IEICE Electron. Express, 2007

2006
Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology.
IEICE Trans. Electron., 2006


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