Satoshi Tayu

According to our database1, Satoshi Tayu authored at least 35 papers between 1999 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2017
Stable Matchings in Trees.
Proceedings of the Computing and Combinatorics - 23rd International Conference, 2017

2016
On the Three-Dimensional Channel Routing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

On orthogonal ray trees.
Discret. Appl. Math., 2016

2015
Dominating Sets in Two-Directional Orthogonal Ray Graphs.
IEICE Trans. Inf. Syst., 2015

OBDD Representation of Intersection Graphs.
IEICE Trans. Inf. Syst., 2015

A Note on Harmonious Coloring of Caterpillars.
IEICE Trans. Inf. Syst., 2015

On Evasion Games on Graphs.
Proceedings of the Discrete and Computational Geometry and Graphs - 18th Japan Conference, 2015

2014
Dominating Sets and Induced Matchings in Orthogonal Ray Graphs.
IEICE Trans. Inf. Syst., 2014

Weighted dominating sets and induced matchings in orthogonal ray graphs.
Proceedings of the International Conference on Control, 2014

A note on the energy-aware mapping for NoCs.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
On Minimum Feedback Vertex Sets in Bipartite Graphs and Degree-Constraint Graphs.
IEICE Trans. Inf. Syst., 2013

2012
Bandwidth of convex bipartite graphs and related graphs.
Inf. Process. Lett., 2012

On Minimum Feedback Vertex Sets in Graphs.
Proceedings of the Third International Conference on Networking and Computing, 2012

2011
On Two Problems of Nano-PLA Design.
IEICE Trans. Inf. Syst., 2011

2010
On orthogonal ray graphs.
Discret. Appl. Math., 2010

On two-directional orthogonal ray graphs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Universal Test Sets for Reversible Circuits.
Proceedings of the Computing and Combinatorics, 16th Annual International Conference, 2010

2009
On the two-dimensional orthogonal drawing of series-parallel graphs.
Discret. Appl. Math., 2009

On the Three-dimensional Orthogonal Drawing of Outerplanar Graphs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Orthogonal Ray Graphs and Nano-PLA Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Cost-Constrained Minimum-Delay Multicasting.
J. Interconnect. Networks, 2008

On Fault Testing for Reversible Circuits.
IEICE Trans. Inf. Syst., 2008

On the three-dimensional orthogonal drawing of series-parallel graphs (extended abstract).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
On the Complexity of Three-Dimensional Channel Routing (Extended Abstract).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
On the Orthogonal Drawing of Outerplanar Graphs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

On the three-dimensional channel routing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
A simulated annealing approach with sequence-pair encoding using a penalty function for the placement problem with boundary constraints.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Characterization and Computation of Steiner Routing Based on Elmore's Delay Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Scheduling Trees onto Hypercubes and Grids.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

3D scheduling based on code space exploration for dynamically reconfigurable systems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Characterization and computation of Steiner wiring based on Elmore's delay model.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2000
An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays.
Proceedings of the 5th International Symposium on Parallel Architectures, 2000

Exact and heuristic methods of assignment driven scheduling for data-path synthesis applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
Scheduling Trees onto Hypercubes and Grids Is NP-complete.
Proceedings of the Computing and Combinatorics, 5th Annual International Conference, 1999


  Loading...