Mineo Kaneko

According to our database, Mineo Kaneko authored at least 92 papers between 1993 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits.

Yuya Ushioda, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024

2023

Optimal Location and Sizing of Renewable Distributed Generators for Improving Robust Voltage Stability Against Uncontrollable Reactive Compensation.

Akanit Kwangkaew, Siriya Skolthanarat, Chalie Charoenlarpnopparut, Mineo Kaneko

IEEE Access, 2023

Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders.

Mineo Kaneko

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Supply-Dominated Energy Balancing for Periodic Operation of Power System.

Saher Javaid, Mineo Kaneko, Yasuo Tan

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

2022

Three-Dimensional Flexible-Module Placement for Stacked Three-Dimensional Integration.

Tomohiro Noguchi, Omran Hindawi, Mineo Kaneko

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

LP-based Co-optimization of Power Generators and Power Storage Systems under the Condition of Safe Operation.

Saher Javaid, Mineo Kaneko, Yasuo Tan, Nouman Ashraf

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022

Hardware Minimization of Two-Level Adiabatic Logic Based on Weighted Maximum Stable Set Problem.

Yuya Ushioda, Mineo Kaneko

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021

Minimum Structural Transformation in Parallel Prefix Adders and its Application to Search-Based Optimization.

Mineo Kaneko

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Storage Minimization Considering System Conditions of Power Flow System.

Saher Javaid, Mineo Kaneko, Yasuo Tan

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

2020

High Level Congestion Detection from C/C++ Source Code for High Level Synthesis.

Masato Tatsuoka, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

Two-Graph Approach to Temperature Dependent Skew Scheduling.

Mineo Kaneko

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Insertion-Based Procedural Construction and Optimization of Parallel Prefix Adders.

Mineo Kaneko

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

System Condition for Controllable Power Flow System Considering Reaction Delay.

Saher Javaid, Mineo Kaneko, Yasuo Tan

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2019

A Novel Framework for Procedural Construction of Parallel Prefix Adders.

Mineo Kaneko

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Power Flow Management for Smart Grids: Considering Renewable Energy and Demand Uncertainty.

Saher Javaid, Mineo Kaneko, Yasuo Tan

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

A Linear Programming Model for Power Flow Control Problem Considering Controllable and Fluctuating Power Devices.

Saher Javaid, Mineo Kaneko, Yasuo Tan

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

2018

Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing.

Takayuki Moto, Mineo Kaneko

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Wire congestion aware high level synthesis flow with source code compiler.

Masato Tatsuoka, Mineo Kaneko

Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2017

Latency-Aware Selection of Check Variables for Soft-Error Tolerant Datapath Synthesis.

Junghoon Oh, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Foreword.

Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

A random access analog memory with master-slave structure for implementing hexadecimal logic.

Renyuan Zhang, Mineo Kaneko

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Margin aware timing test and tuning algorithm for post-silicon skew tuning.

Mineo Kaneko

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

KKT-condition inspired solution of DVFS with limited number of voltage levels.

Mineo Kaneko

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing.

Junghoon Oh, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components.

Junghoon Oh, Mineo Kaneko

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A 16-valued logic FPGA architecture employing analog memory circuit.

Renyuan Zhang, Mineo Kaneko

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Mixed error correction scheme and its design optimization for soft-error tolerant datapaths.

Junghoon Oh, Mineo Kaneko

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

KKT-condition based study on DVFS for heterogeneous task set.

Mineo Kaneko

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism.

Renyuan Zhang, Mineo Kaneko

ACM Trans. Design Autom. Electr. Syst., 2015

Bitwidth-aware register allocation and binding for clock period minimization.

Keisuke Inoue, Mineo Kaneko

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A feasibility study of quaternary FPGA designs by implementing Neuron-MOS mechanism.

Renyuan Zhang, Mineo Kaneko

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis.

Junghoon Oh, Mineo Kaneko

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling.

Mineo Kaneko

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Priority based maximum consuming power control in smart homes.

Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim

Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2014

Constrained binding and scheduling of triplicated algorithm for fault tolerant datapath synthesis.

Mineo Kaneko, Yutaka Tsuboishi

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An ILP-Based Optimal Circuit Mapping Method for PLDs.

Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

A feasibility study on robust programmable delay element design based on neuron-MOS mechanism.

Renyuan Zhang, Mineo Kaneko

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract].

Mineo Kaneko

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle.

Keisuke Inoue, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches.

Keisuke Inoue, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2012

A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths.

Keisuke Inoue, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis.

Keisuke Inoue, Mineo Kaneko

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis.

Keisuke Inoue, Mineo Kaneko

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Post-silicon skew tuning algorithm utilizing setup and hold timing tests.

Mineo Kaneko, Jian Li

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis.

Keisuke Inoue, Mineo Kaneko

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Timing-test scheduling for constraint-graph based post-silicon skew tuning.

Mineo Kaneko

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

An efficient approach for designing and minimizing reversible programmable logic arrays.

Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, Hafiz Md. Hasan Babu

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis.

Keisuke Inoue, Mineo Kaneko

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range.

Keisuke Inoue, Mineo Kaneko

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation.

Keisuke Inoue, Mineo Kaneko

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer.

Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis.

Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Early planning for RT-level delay insertion during clock skew-aware register binding.

Keisuke Inoue, Mineo Kaneko

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A complete framework of simultaneous functional unit and register binding with skew scheduling.

Mineo Kaneko

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis.

Keisuke Inoue, Mineo Kaneko

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Ordered coloring-based resource binding for datapaths with improved skew-adjustability.

Mineo Kaneko, Keisuke Inoue

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths.

Keisuke Inoue, Mineo Kaneko

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties.

Tsuyoshi Iwagaki, Mineo Kaneko

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Optimal register assignment with minimum-delay compensation for latch-based design.

Keisuke Inoue, Mineo Kaneko

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths.

Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

On the derivation of a minimum test set in high quality transition testing.

Tsuyoshi Iwagaki, Mineo Kaneko

Proceedings of the 10th Latin American Test Workshop, 2009

Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis.

Takayuki Obata, Mineo Kaneko

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Safe clocking for the setup and hold timing constraints in datapath synthesis.

Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis.

Takayuki Obata, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Novel Register Sharing in Datapath for Structural Robustness against Delay Variation.

Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Concurrent skew and control step assignments in RT-level datapath synthesis.

Takayuki Obata, Mineo Kaneko

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Safe clocking register assignment in datapath synthesis.

Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki

Proceedings of the 26th International Conference on Computer Design, 2008

2007

Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems.

Koji Ohashi, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Efficient path delay test generation based on stuck-at test generation using checker circuitry.

Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath.

Koji Ohashi, Mineo Kaneko

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules.

Mineo Kaneko

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Statistical schedule length analysis in asynchronous datapath synthesis.

Koji Ohashi, Mineo Kaneko

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Statistical Analysis Driven Synthesis of Asynchronous Systems.

Koji Ohashi, Mineo Kaneko

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2003

Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism.

Mineo Kaneko, Kazuaki Oshio

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis.

Toshiyuki Yorozuya, Koji Ohashi, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Characterization and Computation of Steiner Routing Based on Elmore's Delay Model.

Satoshi Tayu, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Heuristic assignment-driven scheduling for data-path synthesis.

Koji Ohashi, Mineo Kaneko

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

3D scheduling based on code space exploration for dynamically reconfigurable systems.

Mineo Kaneko, Jun'ichi Yokoyama, Satoshi Tayu

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Characterization and computation of Steiner wiring based on Elmore's delay model.

Satoshi Tayu, Mineo Kaneko

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Two-dimensional placement method based on divide-and-replacement.

Yasuhiro Takashima, Akira Kaneko, Shinji Sato, Mineo Kaneko

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Extended dimensional threshold filtering-a bridge between FIR filter and median type filter.

Mineo Kaneko, Yasuaki Maekawa

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays.

Satoshi Tayu, Motoyasu Katsura, Mineo Kaneko

Proceedings of the 5th International Symposium on Parallel Architectures, 2000

An efficient scheme based on EMPDC graph model in synthesizing fault tolerant FIR filter.

Choon-Sik Park, Mineo Kaneko

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Exact and heuristic methods of assignment driven scheduling for data-path synthesis applications.

Mineo Kaneko, Yoshitaka Nishio, Satoshi Tayu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis.

Koji Ohashi, Mineo Kaneko, Satoshi Tayu

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999

Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power.

Mineo Kaneko

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

VLSI/PCB placement with obstacles based on sequence pair.

Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997

Adaptive AR spectral estimation based on multi-band decomposition of the linear prediction error with variable forgetting factors.

Fernando Gil Vianna Resende Jr., Paulo S. R. Diniz, Mineo Kaneko, Akinori Nishihara

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1994

A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural Approach.

Sarwono Sutikno, Mineo Kaneko, Mahoki Onoda

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

AR Spectrum Estimation Based on Wavelet Representation.

Fernando Gil Resende, Keiichi Tokuda, Mineo Kaneko

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation Model.

Mineo Kaneko, Kazuhiro Sakaguchi

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

A Novel Capacitor Placement Strategy in ASCCOT: Automatic Layouter for Switched Capacitor Circuits.

Mineo Kaneko, Masahiro Masuda, Tomohiro Hayashi

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993