Satyasai Evani

According to our database, Satyasai Evani authored at least 2 papers between 2011 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops.

Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2011

A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS.

Biman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011