Krishnaswamy Nagaraj

According to our database1, Krishnaswamy Nagaraj authored at least 22 papers between 1995 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops.
ACM Trans. Design Autom. Electr. Syst., 2021

2019
Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection.
Proceedings of the 24th IEEE European Test Symposium, 2019

2017
A 12-/14-bit, 4/2MSPS, 0.085mm<sup>2</sup> SAR ADC in 65nm using novel residue boosting.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
An oxide electrothermal filter in standard CMOS.
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016

2015
An Embedded 65 nm CMOS Remote Temperature Sensor With Digital Beta Correction and Series Resistance Cancellation Achieving an Inaccuracy of 0.4<sup>°</sup>C (3σ) From - 40<sup>°</sup>C to 130<sup>°</sup>C.
IEEE J. Solid State Circuits, 2015

2014
Corrections to "Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference".
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A Novel fractional-n PLL Based on a Simple Reference Multiplier.
J. Circuits Syst. Comput., 2012

2011
A Two-Stage ADC Architecture With VCO-Based Second Stage.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

2007
Message from the Outgoing Editor-in-Chief.
IEEE J. Solid State Circuits, 2007

New Associate Editors.
IEEE J. Solid State Circuits, 2007

2005
New Associate Editor.
IEEE J. Solid State Circuits, 2005

2004
Editorial.
IEEE J. Solid State Circuits, 2004

2001
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
Widely programmable high-frequency continuous-time filters in digital CMOS technology.
IEEE J. Solid State Circuits, 2000

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process.
IEEE J. Solid State Circuits, 2000

1999
Modeling of accumulation MOS capacitors for analog design in digital VLSI processes.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997
A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers.
IEEE J. Solid State Circuits, 1997

A 160-MHz analog equalizer for magnetic disk read Channel.
IEEE J. Solid State Circuits, 1997

1995
A low supply voltage high PSRR voltage reference in CMOS process.
IEEE J. Solid State Circuits, May, 1995


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