Baher Haroun

According to our database1, Baher Haroun authored at least 33 papers between 1988 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2010, "For development of submicron digital complementary metal-oxide semiconductor for wireless systems-on-chip".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider Achieving 4ppm Frequency Stability over Temperature and <95fs Jitter.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
A Sub-100 Fs RMS<sub>jitter</sub> 20 GHz Fractional-N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference.
IEEE J. Solid State Circuits, 2022

A Duty-Cycled Integrated-Fluxgate Magnetometer for Current Sensing.
IEEE J. Solid State Circuits, 2022

High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation.
IEEE J. Solid State Circuits, 2022

2021
A 770 kS/s Duty-Cycled Integrated-Fluxgate Magnetometer for Contactless Current Sensing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

An Ultra-Low Close-In Phase Noise Series-Resonance BAW Oscillator in a 130-nm BiCMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
3.1 An Integrated BAW Oscillator with <±30ppm Frequency Stability Over Temperature, Package Stress, and Aging Suitable for High-Volume Production.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018
Autonomous Vehicles SEnsor Needs.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017
A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2015
A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications.
IEEE J. Solid State Circuits, 2015

A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners.
IEEE J. Solid State Circuits, 2015

2014
A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS.
IEEE J. Solid State Circuits, 2014

A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS.
Proceedings of the ESSCIRC 2014, 2014

2013
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
Low power ADC's for wireless communications.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 20mW 61dB SNDR (60MHz BW) 1b 3<sup>rd</sup>-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Session 16 overview: Switching power control techniques: Analog subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2010
A 0.16mm<sup>2</sup> completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2006
A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS.
EURASIP J. Wirel. Commun. Netw., 2006

2002
An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique.
IEEE J. Solid State Circuits, 2002

A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

1995
Floorplanning with Datapath Optimization.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994
A Floorplanner driven by Structural & Timing Constraints.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1992
Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Power estimation tool for sub-micron CMOS VLSI circuits.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1989
Architectural synthesis for DSP silicon compilers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988
Automatic synthesis of a multi-bus architecture for DSP.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988


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