Satyendra Biswas

Orcid: 0000-0002-5334-0784

According to our database1, Satyendra Biswas authored at least 21 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Comparative Study and Design of Current Starved Ring Oscillators in 16 nm Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

An Optimized Tongue Drive System for Disabled Persons.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2021

2020
A Robust DWT-Based Compressed Domain Video Watermarking Technique.
Int. J. Image Graph., 2020

2019
Face Identification Based on Discrete Wavelet Transform and Neural Networks.
Int. J. Image Graph., 2019

Analysis and Design of a 32nm FinFET Dynamic Latch Comparator.
CoRR, 2019

2018
Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2016
Short duration voice data speaker recognition system using novel fuzzy vector quantization algorithm.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2016

An algorithm for generating prime implicants.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2016

A compact multispectral image capture unit for deployment on drones.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2016

2015
Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations.
Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015

Image processing based system for classification of vehicles for parking purposes.
Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015

2014
On System-on-Chip Testing Using Hybrid Test Vector Compression.
IEEE Trans. Instrum. Meas., 2014

Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014

2013
Data compression using mixed cascade of nonlinear logic.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2013

Compressed video watermarking technique.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2013

2008
On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing.
IEEE Trans. Instrum. Meas., 2008

Aliasing-free compaction revisited.
IET Circuits Devices Syst., 2008

A Novel Technique for Input Vector Compression in System-on-Chip Testing.
Proceedings of the 2008 International Conference on Information Technology, 2008

2007
Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach.
IEEE Trans. Instrum. Meas., 2007

2006
Space compactor design in VLSI circuits based on graph theoretic concepts.
IEEE Trans. Instrum. Meas., 2006

2005
An adaptive compressed MPEG-2 video watermarking scheme.
IEEE Trans. Instrum. Meas., 2005


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