Wen-Ben Jone

According to our database, Wen-Ben Jone authored at least 112 papers between 1989 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

SERA: statistical error rate analysis for profit-oriented performance binning of resilient circuits.

Qiang Han, Qiang Xu, Wen-Ben Jone

Integr., 2018

2017

Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control.

Yin-Chi Peng, Chien-Chih Chen, Hsiang-Jen Tsai, Keng-Hao Yang, Pei-Zhe Huang, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen

ACM Trans. Design Autom. Electr. Syst., 2017

2016

High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols.

Hsuan-Ming Chou, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability.

Hsuan-Ming Chou, Ming-Yi Hsiao, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Chiao-Ling Lung, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen

IEEE Trans. Very Large Scale Integr. Syst., 2015

On Resilient System Performance Binning.

Qiang Han, Jianghao Guo, Qiang Xu, Wen-Ben Jone

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

2014

On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield.

Tak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

Testing of Synchronizers in Asynchronous FIFO.

Hyoung-Kook Kim, Laung-Terng Wang, Yu-Liang Wu, Wen-Ben Jone

J. Electron. Test., 2013

A configurable bus-tracer for error reproduction in post-silicon validation.

Shing-Yu Chen, Ming-Yi Hsiao, Wen-Ben Jone, Tien-Fu Chen

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Path delay testing in resilient system.

Qiang Han, Jianghao Guo, Wen-Ben Jone, Qiang Xu

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A cross-layer fault-tolerant design method for high manufacturing yield and system reliability.

Jianghao Guo, Qiang Han, Wen-Ben Jone, Yu-Liang Wu

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

On testing timing-speculative circuits.

Feng Yuan, Yannan Liu, Wen-Ben Jone, Qiang Xu

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Post-placement voltage island generation for timing-speculative circuits.

Rong Ye, Feng Yuan, Zelong Sun, Wen-Ben Jone, Qiang Xu

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang

ACM Trans. Design Autom. Electr. Syst., 2012

IMITATOR: A deterministic multicore replay system with refining techniques.

Shing-Yu Chen, Chi-Neng Wen, Geng-Hau Yang, Wen-Ben Jone, Tien-Fu Chen

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011

Dynamic Characteristics of Power Gating During Mode Transition.

Hao Xu, Ranga Vemuri, Wen-Ben Jone

IEEE Trans. Very Large Scale Integr. Syst., 2011

Aggressive Runtime Leakage Control Through Adaptive Light-Weight V_th Hopping With Temperature and Process Variation.

Hao Xu, Wen-Ben Jone, Ranga Vemuri

IEEE Trans. Very Large Scale Integr. Syst., 2011

Location Cache Design and Performance Analysis for Chip Multiprocessors.

Jason Nemeth, Rui Min, Wen-Ben Jone, Yiming Hu

IEEE Trans. Very Large Scale Integr. Syst., 2011

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.

Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Tuning <i>V</i>th Hopping for Aggressive Runtime Leakage Control.

Hao Xu, Wen-Ben Jone, Ranga Vemuri

J. Low Power Electron., 2010

Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer.

Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang

J. Electron. Test., 2010

Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control.

Hao Xu, Wen-Ben Jone, Ranga Vemuri

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs.

Hao Xu, Ranga Vemuri, Wen-Ben Jone

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping.

Hao Xu, Wen-Ben Jone, Ranga Vemuri

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.

Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

Turbo1500: Core-Based Design for Test and Diagnosis.

Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li

IEEE Des. Test Comput., 2009

Temporal and spatial idleness exploitation for optimal-grained leakage control.

Hao Xu, Ranga Vemuri, Wen-Ben Jone

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Analysis of Resistive Open Defects in a Synchronizer.

Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage.

Hao Xu, Ranga Vemuri, Wen-Ben Jone

Proceedings of the Design, Automation and Test in Europe, 2009

Analysis of Resistive Bridging Defects in a Synchronizer.

Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing.

Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Mehmet Sahinoglu

IEEE Trans. Instrum. Meas., 2008

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.

Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li

Proceedings of the 2008 IEEE International Test Conference, 2008

Dynamic virtual ground voltage estimation for power gating.

Hao Xu, Ranga Vemuri, Wen-Ben Jone

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW.

Hao Xu, Ranga Vemuri, Wen-Ben Jone

Proceedings of the 26th International Conference on Computer Design, 2008

Accurate energy breakeven time estimation for run-time power gating.

Hao Xu, Wen-Ben Jone, Ranga Vemuri

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Material Fatigue and Reliability of MEMS Accelerometers.

Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Control Circuitry for Self-Repairable MEMS Accelerometers.

Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone

Proceedings of the Technological Developments in Education and Automation, 2008

2007

Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach.

Sunil R. Das, Jila Zakizadeh, Satyendra Biswas, Mansour H. Assaf, Amiya Nayak, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu

IEEE Trans. Instrum. Meas., 2007

Fault Modeling and Detection for Drowsy SRAM Caches.

Wei Pei, Wen-Ben Jone, Yiming Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects.

Jianxun Liu, Wen-Ben Jone

Proceedings of the 25th International Conference on Computer Design, 2007

2006

Crosstalk test pattern generation for dynamic programmable logic arrays.

Jianxun Liu, Wen-Ben Jone, Sunil R. Das

IEEE Trans. Instrum. Meas., 2006

An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing.

Ming Li, Wen-Ben Jone, Qing-An Zeng

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Reliability Analysis of Self-Repairable MEMS Accelerometer.

Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip.

Ming Li, Qing-An Zeng, Wen-Ben Jone

Proceedings of the 43rd Design Automation Conference, 2006

2005

A dual-mode built-in self-test technique for capacitive MEMS devices.

Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone

IEEE Trans. Instrum. Meas., 2005

A built-in self-testing method for embedded multiport memory arrays.

Vinod Narayanan, Swaroop Ghosh, Wen-Ben Jone, Sunil R. Das

IEEE Trans. Instrum. Meas., 2005

Fault simulation and response compaction in full scan circuits using HOPE.

Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu

IEEE Trans. Instrum. Meas., 2005

Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization.

Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu

IEEE Trans. Instrum. Meas., 2005

Design and Analysis of Self-Repairable MEMS Accelerometer.

Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Design and design automation of rectification logic for engineering change.

Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays.

Vikram Arora, Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das

IEEE Trans. Instrum. Meas., 2004

Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs.

Rui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Location cache: a low-power L2 cache system.

Rui Min, Wen-Ben Jone, Yiming Hu

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Phased tag cache: an efficient low power cache system.

Rui Min, Wen-Ben Jone, Yiming Hu

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits.

Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Embedded core test generation using broadcast test architecture and netlist scrambling.

J. H. Jiang, Wen-Ben Jone, Shih-Chieh Chang, Swaroop Ghosh

IEEE Trans. Reliab., 2003

Design theory and implementation for low-power segmented bus systems.

Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen

ACM Trans. Design Autom. Electr. Syst., 2003

An efficient BIST method for non-traditional faults of embedded memory arrays.

Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das

IEEE Trans. Instrum. Meas., 2003

Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets.

Sunil R. Das, Made Sudarma, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Krishnendu Chakrabarty, Mehmet Sahinoglu

IEEE Trans. Instrum. Meas., 2003

2002

An efficient BIST method for distributed small buffers.

Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee

IEEE Trans. Very Large Scale Integr. Syst., 2002

Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering.

Sunil R. Das, Jing Yi Liang, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Krishnendu Chakrabarty

IEEE Trans. Instrum. Meas., 2002

A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations.

Der-Cheng Huang, Wen-Ben Jone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A parallel built-in self-diagnostic method for embedded memoryarrays.

Der-Cheng Huang, Wen-Ben Jone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001

Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis.

Wen-Ben Jone, Der-Cheng Huang, Shih-Chieh Chang, Sunil R. Das

VLSI Design, 2001

Random Pattern Testability Enhancement by Circuit Rewiring.

Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hsiang Cheng, Wen-Ben Jone, Sunil R. Das

VLSI Design, 2001

An adaptive path selection method for delay testing.

Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das

IEEE Trans. Instrum. Meas., 2001

Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities.

Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone

IEEE Trans. Instrum. Meas., 2001

Charge-sharing alleviation and detection for CMOS domino circuits.

Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers.

Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers.

Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Embedded Core Testing Using Broadcast Test Architecture.

J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000

TAIR: testability analysis by implication reasoning.

Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation.

Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.

Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

An efficient parallel transparent diagnostic BIST.

Der-Cheng Huang, Wen-Ben Jone

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Charge sharing fault analysis and testing for CMOS domino logic circuits.

Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Segmented bus design for low-power systems.

J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen

IEEE Trans. Very Large Scale Integr. Syst., 1999

An Efficient BIST Method for Small Buffers.

Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Power reduction through iterative gate sizing and voltage scaling.

Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Charge Sharing Fault Detection for CMOS Domino Logic Circuits.

Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications.

Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone

Proceedings of the 36th Conference on Design Automation, 1999

1998

Syndrome Signature in Output Compaction for VLSI Built-in Self-Test.

Sunil R. Das, Nita Goel, Wen-Ben Jone, Amiya R. Nayak

VLSI Design, 1998

Confidence analysis for defect-level estimation of VLSI random testing.

Wen-Ben Jone, K. S. Tsai

ACM Trans. Design Autom. Electr. Syst., 1998

A Stochastic Method for Defect Level Analysis of Pseudorandom Testing.

Wen-Ben Jone, Sunil R. Das

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.

Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

A novel combinational testability analysis by considering signal correlation.

Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Delay Fault Coverage Enhancement Using Variable Observation Times.

Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das

J. Electron. Test., 1997

Delay Fault Coverage Enhancement Using Multiple Test Observation Times.

Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

PGEN: A Novel Approach to Sequential Circuit Test Generation.

Wen-Ben Jone, Nigam Shah, Anita Gleason, Sunil R. Das

VLSI Design, 1996

Pseudorandom test-length analysis using differential solutions.

Dan Li, Wen-Ben Jone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Syndrome signature in output compaction for VLSI BIST.

Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

Realizing a high measure of confidence for defect level analysis of random testing [VLSI].

Wen-Ben Jone, Paresh Gondalia, Allan Gutjahr

IEEE Trans. Very Large Scale Integr. Syst., 1995

CACOP-a random pattern testability analyzer.

Wen-Ben Jone, Sunil R. Das

IEEE Trans. Syst. Man Cybern., 1995

On testing of sequential machines using circuit decomposition and stochastic modeling.

Sunil R. Das, Wen-Ben Jone, Amiya R. Nayak, Ian Choi

IEEE Trans. Syst. Man Cybern., 1995

A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.

Wen-Ben Jone, Christos A. Papachristou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Timing optimization by gate resizing and critical path identification.

Chen-Liang Fang, Wen-Ben Jone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

An improved output compaction technique for built-in self-test in VLSI circuits.

Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1994

Multiple Fault Detection in Parity Checkers.

Wen-Ben Jone, Cheng-Juei Wu

IEEE Trans. Computers, 1994

On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition.

Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi

Proceedings of the Seventh International Conference on VLSI Design, 1994

Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach.

Amiya R. Nayak, Wen-Ben Jone, Sunil R. Das

Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994

1993

Multiple fault testing using minimal single fault test set for fanout-free circuits.

Wen-Ben Jone, Patrick H. Madden

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Defect level estimation of circuit testing using sequential statistical analysis.

Wen-Ben Jone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing.

Paresh Gondalia, Allan Gutjahr, Wen-Ben Jone

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992

On random testing for combinational circuits with a high measure of confidence.

Sunil R. Das, Wen-Ben Jone

IEEE Trans. Syst. Man Cybern., 1992

1991

Analysis of Hamming count compaction scheme.

Wen-Ben Jone, Anita Gleason

J. Electron. Test., 1991

Defect Level Estimation of Random and Pseudorandom Testing.

Wen-Ben Jone

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Reduced Hamming Count and Its Aliasing Probability.

Anita Gleason, Wen-Ben Jone

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990

Probabilistic modeling and fault analysis in sequential logic using computer simulation.

Sunil R. Das, Wen-Ben Jone, K. L. Wong

IEEE Trans. Syst. Man Cybern., 1990

Multiple-output parity bit signature for exhaustive testing.

Wen-Ben Jone, Sunil R. Das

J. Electron. Test., 1990

1989

Hamming count-a compaction testing technique.

Anita Gleason, Wen-Ben Jone

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

A Scheme for Overlaying Concurrent Testing of VLSI Circuits.

Wen-Ben Jone, Christos A. Papachristou, M. Pereira

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing.

Wen-Ben Jone, Christos A. Papachristou

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989