Satyendra Datla

According to our database, Satyendra Datla authored at least 5 papers between 2010 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage.

Rahul Rithe, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha P. Chandrakasan

IEEE Trans. Very Large Scale Integr. Syst., 2012

A 28 nm 0.6 V Low Power DSP for Mobile Applications.

Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko

IEEE J. Solid State Circuits, 2012

2011

Cell Library Characterization at Low Voltage Using Non-linear Operating Point Analysis of Local Variations.

Rahul Rithe, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha P. Chandrakasan

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A 28nm 0.6V low-power DSP for mobile applications.

Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

Non-linear Operating Point Statistical Analysis for Local Variations in logic timing at low voltage.

Rahul Rithe, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha P. Chandrakasan

Proceedings of the Design, Automation and Test in Europe, 2010