Hugh Mair

According to our database1, Hugh Mair authored at least 21 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
2.1 A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

2021
Session 4 Overview: Processors Digital Architectures and Systems Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

SE1: What Technologies Will Shape the Future of Computing?
Proceedings of the IEEE International Solid-State Circuits Conference, 2021


2020
2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2017
3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Session 17 overview: SRAM.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2012
A 28 nm 0.6 V Low Power DSP for Mobile Applications.
IEEE J. Solid State Circuits, 2012

2011
A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 28nm 0.6V low-power DSP for mobile applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors.
Proc. IEEE, 2010

2008
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Solutions for logic and processor core design at the 45nm technology node & and below.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2005
A design platform for 90-nm leakage reduction techniques.
Proceedings of the 42nd Design Automation Conference, 2005

2000
An architecture of high-performance frequency and phase synthesis.
IEEE J. Solid State Circuits, 2000


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