Mahmut E. Sinangil

According to our database1, Mahmut E. Sinangil authored at least 28 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Online presence:

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Bibliography

2022
A 5-nm 254-TOPS/W 221-TOPS/mm<sup>2</sup> Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS.
IEEE J. Solid State Circuits, 2021

An 89TOPS/W and 16.3TOPS/mm<sup>2</sup> All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell.
IEEE J. Solid State Circuits, 2019

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination.
IEEE J. Solid State Circuits, 2019

2018
A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017
Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics.
IEEE J. Solid State Circuits, 2017

2016
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation.
IEEE J. Solid State Circuits, 2016

Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2014
Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9× Lower Energy/Access.
IEEE J. Solid State Circuits, 2014

A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation.
Proceedings of the Symposium on VLSI Circuits, 2014

A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard.
IEEE J. Sel. Top. Signal Process., 2013

An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Low-power and application-specific SRAM design for energy-efficient motion estimation.
PhD thesis, 2012

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 28 nm 0.6 V Low Power DSP for Mobile Applications.
IEEE J. Solid State Circuits, 2012

Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

Hardware-aware motion estimation search algorithm development for high-efficiency video coding (HEVC) standard.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

Self-aware computing in the Angstrom processor.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Challenges and Directions for Low-Voltage SRAM.
IEEE Des. Test Comput., 2011

A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 28nm 0.6V low-power DSP for mobile applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Technologies for Ultradynamic Voltage Scaling.
Proc. IEEE, 2010

2009
A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder.
IEEE J. Solid State Circuits, 2009

A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS.
IEEE J. Solid State Circuits, 2009

2008
A reconfigurable 65nm SRAM achieving voltage scalability from 0.25-1.2V and performance scalability from 20kHz-200MHz.
Proceedings of the ESSCIRC 2008, 2008


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