Sayan Chatterjee

Orcid: 0000-0002-4494-9029

According to our database1, Sayan Chatterjee authored at least 14 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
The Impact of AI Tool on Engineering at ANZ Bank An Emperical Study on GitHub Copilot within Coporate Environment.
CoRR, 2024

2023
A Multiphase Low Phase-Noise DCO based on Self-Timed Ring Oscillator.
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023

Design of High Gain Low-Noise Amplifier at X-Band Frequency.
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023

Biosensors: Pioneering Progress in Sensing Technologies across Generations.
Proceedings of the 16th International Conference on Sensing Technology, 2023

2022
Compact High-Selectivity Wide Stopband Microstrip Cross-Coupled Bandpass Filter With Spurline.
IEEE Access, 2022

Logic and Reduction Operation based Hardware Trojans in Digital Design.
Proceedings of the 19th International SoC Design Conference, 2022

2021
Federated Learning for Intrusion Detection in IoT Security: A Hybrid Ensemble Approach.
CoRR, 2021

2020
Economy and Unemployment Due to COVID19: Secondary Research.
Proceedings of the Intelligence Science III: 4th IFIP TC 12 International Conference, 2020

2019
An Online Pattern Based Activity Discovery: In Context of Geriatric Care.
Proceedings of the Computer Information Systems and Industrial Management, 2019

2015
Linear array pattern synthesis using restriction in search space for evolutionary algorithms: A comparative study.
Proceedings of the 2nd IEEE International Conference on Recent Trends in Information Systems, 2015

2013
Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit.
CoRR, 2013

2012
Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications.
Proceedings of the International Symposium on Electronic System Design, 2012

Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme.
Proceedings of the International Symposium on Electronic System Design, 2012


  Loading...