Sayeeda Sultana

According to our database, Sayeeda Sultana authored at least 9 papers between 2006 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Testing reversible adder/subtractor for missing control points.

Sayeeda Sultana, Katarzyna Radecka

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

SAT-based reversible gate/wire replacement fault testing.

Sayeeda Sultana, Atena Roshan Fekr, Katarzyna Radecka

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2011

Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network.

Sayeeda Sultana, Katarzyna Radecka

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

A novel method of synthesizing reversible logic.

Yu Pang, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Reversible implementation of square-root circuit.

Sayeeda Sultana, Katarzyna Radecka

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A study on relating redundancy removal in classical circuits to reversible mapping.

Sayeeda Sultana, Katarzyna Radecka, Yu Pang

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Positive Davio-based synthesis algorithm for reversible logic.

Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2008

Design for Testability of QCA Logic Under Stuck-at-value Fault Model.

Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka

J. Multiple Valued Log. Soft Comput., 2008

2006

Testing QCA Modular Logic.

Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka

Proceedings of the 13th IEEE International Conference on Electronics, 2006