Sebastian Lange

According to our database1, Sebastian Lange authored at least 22 papers between 2003 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2022
Solving Discrete Optimal Power Flow Problem via Power Gird Topology Exploitation.
Proceedings of the 31st IEEE International Symposium on Industrial Electronics, 2022

2021
Datenschutzfreundliche Algorithmen.
Datenschutz und Datensicherheit, 2021

2019
Using revealed-bidding in power markets: A paradigmatic model.
Proceedings of the 28th IEEE International Symposium on Industrial Electronics, 2019

Descending-clock reverse auction for electricity markets considering power flow constraints.
Proceedings of the IECON 2019, 2019

2013
Particle Simulation in Turbulent Plasmas with Amplified Wavemodes.
Proceedings of the High Performance Computing in Science and Engineering '13, 2013

2010
From today's INTRAnet of things to a future INTERnet of things: a wireless- and mobility-related view.
IEEE Wirel. Commun., 2010

Multi-level reconfigurable architectures in the switch model.
J. Syst. Archit., 2010

Models and Algorithms for Hyperreconfigurable Hardware.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2008
Hyperreconfigurable systems: formal concepts, architectures, and applications.
PhD thesis, 2008

Design Aspects of Multi-level Reconfigurable Architectures.
J. Signal Process. Syst., 2008

Hyperreconfigurable architectures.
Proceedings of the FPL 2008, 2008

2006
Granularity aspects for the design of multi-level reconfigurable architectures.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Cache Architectures for Reconfigurable Hardware.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

2005
Hyperreconfigurable architectures and the partition into hypercontexts problem.
J. Parallel Distributed Comput., 2005

Multi task hyperreconfigurable architectures: models and reconfiguration problems.
Int. J. Embed. Syst., 2005

On the design of two-level reconfigurable architectures.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

Heuristics for Context-Caches in 2-Level Reconfigurable Architectures.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004
Models and Reconfiguration Problems for Multi Task Hyperreconfigurable Architectures.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 2004

Hyperreconfigurable Architectures for Fast Run Time Reconfiguration.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Hyperreconfigurable Architectures as Flexible Control Systems.
Proceedings of the ARCS 2004, 2004

2003
Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems.
Proceedings of the 2003 Design, 2003


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