Udo Kebschull

Affiliations:
  • Goethe University Frankfurt am Main, Germany


According to our database1, Udo Kebschull authored at least 37 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
DFTWS for blockchain: Deterministic, Fair and Transparent Winner Selection.
CoRR, 2023

HEPchain: Novel Proof-of-Useful-Work blockchain consensus for High Energy Physics.
CoRR, 2023

2018
Arhuaco: Deep Learning and Isolation Based Security for Distributed High-Throughput Computing.
CoRR, 2018

2017
A Security Monitoring Framework For Virtualization Based HEP Infrastructures.
CoRR, 2017

Intrusion Prevention and Detection in Grid Computing - The ALICE Case.
CoRR, 2017

Highly Parallel Lattice QCD Wilson Dirac Operator with FPGAs.
Proceedings of the Parallel Computing is Everywhere, 2017

2015
A resilient, flash-free soft error mitigation concept for the CBM-ToF read-out chain via GBT-SCA.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Biomedical image processing and reconstruction with dataflow computing on FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Bitfile preservation - Generation of reusable out of context modules.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Radiation mitigation efficiency of scrubbing on the FPGA based CBM-TOF read-out controller.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
An implementation of 3D Electron Tomography on FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

2011
Accelerating Image Analysis for Localization Microscopy with FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
FPGA Fault Tolerance in Particle Physics Experiments (FPGA Fehlertoleranz bei Experimenten in der Teilchenphysik).
it Inf. Technol., 2010

Selected papers from the 18<sup>th</sup> International Conference on Field Programmable Logic and Applications (FPL 2008) [Editorial].
IET Comput. Digit. Tech., 2010

2009
An approach to system-wide fault tolerance for FPGAs.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

DPR in high energy physics.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Fast SIMDized Kalman filter based track fit.
Comput. Phys. Commun., 2008

Parallel hardware objects for dynamically partial reconfiguration.
Proceedings of the FPL 2008, 2008

2006
Applications of FPGA Reconfiguration for Experiments in High Energy Physics.
Proceedings of the ARCS 2006, 2006

2005
Optimization of Start-Up Time and Quiescent Power Consumption of FPGAs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2003
A Novel Design Technology for Next Generation Ubiquitous Computing Architecture.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems.
Proceedings of the 2003 Design, 2003

2002
The Use of Runtime Configuration Capabilities for Networked Embedded Systems.
Proceedings of the 2002 Design, 2002

2001
Kommerzielle Grossrechner als Ausbildungsaufgabe an Universitäten und Fachhochschulen.
Inform. Spektrum, 2001

2000
Emulation synthetisierter Verhaltensbeschreibungen mit VLIW-Prozessoren.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

A Hardware Platform for VLIW Based Emulation of Digital Designs.
Proceedings of the 2000 Design, 2000

1999
Ein Branch & Bound-Ansatz zur Verdrahtung von Field Programmable Gate-Arrays.
Informationstechnik Tech. Inform., 1999

Beschreibung und Simulation von Hardware/Software-Systemen mit Java.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999

Description and Simulation of Hardware/Software Systems with Java.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Breakpoints and breakpoint detection in source-level emulation.
ACM Trans. Design Autom. Electr. Syst., 1998

Behavioral Emulation of Synthesized RT-Level Descriptions Using VLIW Architectures.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

1997
Co-Emulation and Debugging of HW/SW-Systems.
Proceedings of the 10th International Symposium on System Synthesis, 1997

1996
System prototyping in the COBRA project.
Microprocess. Microsystems, 1996

Library based technology mapping using multiple domain representations.
Proceedings of the conference on European design automation, 1996

1995
Verhaltensbasierte und spektrale Logiksynthese mehrstufiger Schaltnetze unter Verwendung von Binärbäumen
PhD thesis, 1995

Debugging of behavioral VHDL specifications by source level emulation.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
A prototyping environment for hardware/software codesign in the COBRA project.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994


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