Seiji Uenohara

According to our database, Seiji Uenohara authored at least 6 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation.

Fuyuki Kihara, Seiji Uenohara, Satoshi Awamura, Naoko Misawa, Chihiro Matsui, Ken Takeuchi

CoRR, July, 2025

CuLD: Current-Limiting Differential Reading Circuit for Current-Based Compute-in-Memory.

Seiji Uenohara, Satoshi Awamura, Norio Hattori

CoRR, February, 2025

2023

A Trainable Synapse Circuit Using a Time-Domain Digital-to-Analog Converter.

Seiji Uenohara, Kazuyuki Aihara

Circuits Syst. Signal Process., March, 2023

2022

A 18.7 TOPS/W Mixed-Signal Spiking Neural Network Processor With 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain.

Seiji Uenohara, Kazuyuki Aihara

IEEE Access, 2022

2021

Time-Domain Digital-to-Analog Converter for Spiking Neural Network Hardware.

Seiji Uenohara, Kazuyuki Aihara

Circuits Syst. Signal Process., 2021

CMOS Mixed-Signal Spiking Neural Network Circuit Using a Time-Domain Digital-To-Analog Converter.

Seiji Uenohara, Kazuyuki Aihara

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021