Chihiro Matsui
Orcid: 0000-0003-4594-6839
According to our database1,
Chihiro Matsui
authored at least 34 papers
between 2016 and 2024.
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Bibliography
2024
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024
2023
Write Variation & Reliability Error Compensation by Layer-Wise Tunable Retraining of Edge FeFET LM-GA CiM.
IEICE Trans. Electron., July, 2023
Heterogeneous Integration of Precise and Approximate Storage for Error-Tolerant Workloads.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023
ReRAM CiM Fluctuation Pattern Classification by CNN Trained on Artificially Created Dataset.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance.
Proceedings of the IEEE International Memory Workshop, 2023
LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2022
Edge Computation-in-Memory for In-situ Class-incremental Learning with Knowledge Distillation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Domain Specific ReRAM Computation-in-Memory Design Considering Bit Precision and Memory Errors for Simulated Annealing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Versatile FeFET Voltage-sensing Analog CiM for Fast & Small-area Hyperdimensional Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Edge Retraining of FeFET LM-GA CiM for Write Variation & Reliability Error Compensation.
Proceedings of the IEEE International Memory Workshop, 2022
Non-volatile Memory Application to Quantum Error Correction with Non-uniformly Quantized CiM.
Proceedings of the IEEE International Memory Workshop, 2022
2021
Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory.
Proceedings of the IEEE International Memory Workshop, 2021
2020
Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs).
IEICE Trans. Electron., 2020
System Performance Comparison of 3D Charge-Trap TLC NAND Flash and 2D Floating-Gate MLC NAND Flash Based SSDs.
IEICE Trans. Electron., 2020
Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage.
Integr., 2019
Self-Determining Resource Control in Multi-Tenant Data Center Storage with Future NV Memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Design of heterogeneously-integrated memory system with storage class memories and NAND flash memories.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Reliability Analysis of Scaled NAND Flash Memory Based SSDs with Real Workload Characteristics by Using Real Usage-Based Precise Reliability Test.
IEICE Trans. Electron., 2018
Analysis of SCM-Based SSD Performance in Consideration of SCM Access Unit Size, Write/Read Latencies and Application Request Size.
IEICE Trans. Electron., 2018
Double asymmetric-latency storage class memories (SCMs) for fast-write SCM, fast-read SCM & NAND flash hybrid SSDs.
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Periodic Data Eviction Algorithm of SCM/NAND Flash Hybrid SSD with SCM Retention Time Constraint Capabilities at Extremely High Temperature.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
Maximizing Peformance/cost Figure of Merit of Storage-type SCM based SSD by Adding Small Capacity of Memory-type SCM.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proc. IEEE, 2017
Workload-Based Co-Design of Non-Volatile Cache Algorithm and Storage Class Memory Specifications for Storage Class Memory/NAND Flash Hybrid SSDs.
IEICE Trans. Electron., 2017
22% Higher performance, 2x SCM write endurance heterogeneous storage with dual storage class memory and NAND flash.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2016
LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives.
IEEE Trans. Very Large Scale Integr. Syst., 2016