Seung H. Hwang

According to our database1, Seung H. Hwang authored at least 3 papers between 1998 and 2000.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2000
A Reliability Testing Environment for Off-the-Shelf Memory Subsystems.
IEEE Design & Test of Computers, 2000

1999
Selective-set-invalidation (SSI) for soft-error-resilient cache architecture.
SIGARCH Computer Architecture News, 1999

1998
On-Chip Cache Memory Resilience.
Proceedings of the 3rd IEEE International Symposium on High-Assurance Systems Engineering (HASE '98), 1998


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