Gwan S. Choi

According to our database1, Gwan S. Choi authored at least 73 papers between 1992 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

2017
The Normalized Singular Value Decomposition of Non-Symmetric Matrices Using Givens fast Rotations.
CoRR, 2017

2016
Hardware Architecture of Complex K-best MIMO Decoder.
CoRR, 2016

An Encoding Scheme with Constituent Codes Optimization for Polar Code-Aim to Reduce the Decoding Latency.
CoRR, 2016

An Efficient Partial Sums Generator for Constituent Code based Successive Cancellation Decoding of Polar Codes.
CoRR, 2016

Overlapped list successive cancellation approach for hardware efficient polar code decoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

TC: Throughput centric successive cancellation decoder hardware implementation for polar codes.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

2015
Accelerated Dual-Path Asynchronous Circuit.
IEEE Trans. on Circuits and Systems, 2015

Fixed Point Realization of Iterative LR-Aided Soft MIMO Decoding Algorithm.
CoRR, 2015

Compressive sensing and reception for MIMO-OFDM based cognitive radio.
Proceedings of the International Conference on Computing, Networking and Communications, 2015

An iterative LR-aided MMSE extended soft MIMO decoding algorithm.
Proceedings of the International Conference on Computing, Networking and Communications, 2015

XJ-BP: Express Journey Belief Propagation Decoding for Polar Codes.
Proceedings of the 2015 IEEE Global Communications Conference, 2015

2014
WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture.
ACM Trans. Design Autom. Electr. Syst., 2014

Signal reconstruction processor design for compressive sensing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Asynchronous design for precision-scaleable energy-efficient LDPC decoder.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

An iterative soft decision based adaptive K-best decoder without SNR estimation.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
Support Vector Machine Based Detection of Drowsiness Using Minimum EEG Features.
Proceedings of the International Conference on Social Computing, SocialCom 2013, 2013

Bidirectional interconnect design for low latency high bandwidth NoC.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012
Unequal Error Protection Based on DVFS for JSCD in Low-Power Portable Multimedia Systems.
ACM Trans. Embedded Comput. Syst., 2012

Exploiting path diversity for low-latency and high-bandwidth with the dual-path NoC router.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Design space exploration for low-power channel decoder in embedded LDPC-H.264 joint decoding architecture.
IJITCC, 2011

Low-Power, Resilient Interconnection with Orthogonal Latin Squares.
IEEE Design & Test of Computers, 2011

Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system.
Proceedings of the 48th Design Automation Conference, 2011

2010
Low-power baseband processing for wireless multimedia systems using unequal error protection.
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs.
Proceedings of the NOCS 2010, 2010

2009
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics.
IEEE Trans. VLSI Syst., 2009

Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels.
J. Low Power Electronics, 2009

Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes".
EURASIP J. Emb. Sys., 2009

Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

SEU hardened clock regeneration circuits.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Systolic like soft-detection architecture for 4×4 64-QAM MIMO system.
Proceedings of the Design, Automation and Test in Europe, 2009

Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Data Handling Limits of On-Chip Interconnects.
IEEE Trans. VLSI Syst., 2008

Architecture for reconfigurable MIMO detector and its FPGA implementation.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Dynamically reconfigurable soft output MIMO detector.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Speculative Energy Scheduling for LDPC Decoding.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax.
Proceedings of IEEE International Conference on Communications, 2007

An FPGA Implementation of Dirty Paper Precoder.
Proceedings of IEEE International Conference on Communications, 2007

Minimum-energy LDPC decoder for real-time mobile application.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Information theoretic approach to address delay and reliability in long on-chip interconnects.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Timing Failure Analysis of Commercial CPUs Under Operating Stress.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

A design approach for radiation-hard digital electronics.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Quantized LDPC decoder design for binary symmetric channels.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

FPGA based implementation of decoder for array low-density parity-check codes.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

2004
Scaleable check node centric architecture for LDPC decoder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Fast Simulation Technique for LDPC Code Analysis.
Proceedings of the International Conference on Wireless Networks, 2004

An LDPC decoding schedule for memory access reduction.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
A massively scaleable decoder architecture for low-density parity-check codes.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2001
ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Simulation Using Code-Perturbation: Black- and White-Box Approach.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

An On-Line Testing Approach Using Code-Perturbation.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

RTL functional verification using excitation and observation coverage.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

2000
Verification Simulation Acceleration Using Code-Perturbation.
J. Electronic Testing, 2000

A Reliability Testing Environment for Off-the-Shelf Memory Subsystems.
IEEE Design & Test of Computers, 2000

Si-emulation: system verification using simulation and emulation.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Selective-set-invalidation (SSI) for soft-error-resilient cache architecture.
SIGARCH Computer Architecture News, 1999

1998
Error and Failure Analysis of a UNIX Server.
Proceedings of the 3rd IEEE International Symposium on High-Assurance Systems Engineering (HASE '98), 1998

On-Chip Cache Memory Resilience.
Proceedings of the 3rd IEEE International Symposium on High-Assurance Systems Engineering (HASE '98), 1998

1996
A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults.
IEEE Trans. Computers, 1996

1994
Device-Level Transient Fault Modeling.
Proceedings of the Digest of Papers: FTCS/24, 1994

1993
Fault behavior dictionary for simulation of device-level transients.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Wear-Out Simulation Environment for VLSI Designs.
Proceedings of the Digest of Papers: FTCS-23, 1993

A Fast and Accurate Gate-Level Transient Fault Simulation Environment.
Proceedings of the Digest of Papers: FTCS-23, 1993

1992
FOCUS: An Experimental Environment for Fault Sensitivity Analysis.
IEEE Trans. Computers, 1992


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