Seyed Nematollah Ahmadyan

Orcid: 0000-0001-8987-1475

According to our database1, Seyed Nematollah Ahmadyan authored at least 10 papers between 2012 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
A novel test compression algorithm for analog circuits to decrease production costs.
Integr., 2017

2016
Automated Transient Input Stimuli Generation for Analog Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Duplex: simultaneous parameter-performance exploration for optimizing analog circuits.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A random tree search algorithm for Nash equilibrium in capacitated selfish replication games.
Proceedings of the 55th IEEE Conference on Decision and Control, 2016

Every test makes a difference: Compressing analog tests to decrease production costs.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Fast eye diagram analysis for high-speed CMOS circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013
Reachability analysis of nonlinear analog circuits through iterative reachable set reduction.
Proceedings of the Design, Automation and Test in Europe, 2013

Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Goal-oriented stimulus generation for analog circuits.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012


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