Jayanand Asok Kumar

According to our database1, Jayanand Asok Kumar authored at least 12 papers between 2010 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2014
Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013
Formal Probabilistic Timing Verification in RTL.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Statistical guarantees of performance for RTL designs
PhD thesis, 2012

Formal Performance Analysis for Faulty MIMO Hardware.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Early prediction of NBTI effects using RTL source code analysis.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Goal-oriented stimulus generation for analog circuits.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Verifying dynamic power management schemes using statistical model checking.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Variation-Conscious Formal Timing Verification in RTL.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Scaling probabilistic timing verification of hardware using abstractions in design source code.
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010
Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs.
Proceedings of the QEST 2010, 2010

Statistical guarantees of performance for MIMO designs.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010


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