Shang-Jen Tsai

According to our database, Shang-Jen Tsai authored at least 3 papers between 2015 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures.

Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen

IEEE Trans. Very Large Scale Integr. Syst., 2017

2016

Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors.

Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen

Integr., 2016

2015

A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation.

Yung-Hui Yu, Po-Hao Wang, Shang-Jen Tsai, Tien-Fu Chen

Proceedings of the VLSI Design, Automation and Test, 2015