Shannon V. Morton

According to our database, Shannon V. Morton authored at least 6 papers between 1994 and 2002.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2002

Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU.

Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

1999

On-Chip Inductance Issues in Multiconductor Systems.

Shannon V. Morton

Proceedings of the 36th Conference on Design Automation, 1999

1997

A new method for asynchronous pipeline control.

Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Two-Phase Asynchronous Pipeline Control.

Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt

Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1995

ECSTAC: a fast asynchronous microprocessor.

Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt

Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1994

An event controlled reconfigurable multi-chip FFT.

Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt

Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994