Shi-Huang Yin

According to our database, Shi-Huang Yin authored at least 2 papers between 2002 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2012

A 32-core RISC microprocessor with network accelerators, power management and testability features.

Brian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, David Carlson, Vishnu Yalala, Thucydides Xanthopoulos, Scott E. Meninger, Ethan Crain, Mark Spaeth, Akin Aina, Suresh Balasubramanian, Joe Vulih, Pragati Tiwary, David Lin, Richard Kessler, Bruce Fishbein, Anil Jain

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2002

Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU.

Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002