Shashank Raghuraman

According to our database, Shashank Raghuraman authored at least 7 papers between 2017 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Low-Complex and Low-Power n-dimensional Gram-Schmidt Orthogonalization Architecture Design Methodology.

Swati Bhardwaj, Shashank Raghuraman, Jayesh B. Yerrapragada, Agathya Jagirdar, Koushik Maharatna, Amit Acharyya

Circuits Syst. Signal Process., 2022

2020

Impact of System-on-Chip Integration of AEAD Ciphers.

Shashank Raghuraman, Leyla Nazhandali

IACR Cryptol. ePrint Arch., 2020

2019

Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA.

Swati Bhardwaj, Shashank Raghuraman, Amit Acharyya

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

Vector Cross Product and Coordinate Rotation Based <i>n</i>D Hybrid FastICA.

Swati Bhardwaj, Shashank Raghuraman, Bhagyaraja Adapa, Amit Acharyya

J. Low Power Electron., 2018

2017

Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture.

Bhagyaraja Adapa, Dwaipayan Biswas, Swati Bhardwaj, Shashank Raghuraman, Amit Acharyya, Koushik Maharatna

IEEE Trans. Very Large Scale Integr. Syst., 2017

Low complexity hardware accelerator for nD FastICA based on coordinate rotation.

Swati Bhardwaj, Shashank Raghuraman, Amit Acharyya

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Coordinate rotation and vector cross product based hardware accelerator for nD FastICA.

Swati Bhardwaj, Shashank Raghuraman, Amit Acharyya

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017