Hideki Asai

According to our database, Hideki Asai authored at least 84 papers between 1985 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Accelerating Symmetric Rank-1 Quasi-Newton Method with Nesterov's Gradient for Training Neural Networks.

S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai

Algorithms, 2022

A Stochastic Momentum Accelerated Quasi-Newton Method for Neural Networks (Student Abstract).

S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai

Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

On the Practical Robustness of the Nesterov's Accelerated Quasi-Newton Method.

S. Indrapriyadarsini, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai

Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021

A modified limited memory Nesterov's accelerated quasi-Newton.

S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai

CoRR, 2021

2020

A Nesterov's Accelerated quasi-Newton method for Global Routing using Deep Reinforcement Learning.

S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai

CoRR, 2020

A Neural Network Approach to Analog Circuit Design Optimization using Nesterov's Accelerated Quasi-Newton Method.

S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

An Adaptive Stochastic Nesterov Accelerated Quasi Newton Method for Training RNNs.

S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai

CoRR, 2019

Momentum Acceleration of Quasi-Newton Training for Neural Networks.

Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai

Proceedings of the PRICAI 2019: Trends in Artificial Intelligence, 2019

A Stochastic Quasi-Newton Method with Nesterov's Accelerated Gradient.

S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai

Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2019

A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method.

Sota Yasuda, Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai

Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019

2018

Implementation of a Modified Nesterov's Accelerated Quasi-Newton Method on Tensorflow.

S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai

Proceedings of the 17th IEEE International Conference on Machine Learning and Applications, 2018

2017

SI/PI/EMI simulation techniques and application to automotive electronic design issues.

Hideki Asai

Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

2014

Foreword.

Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission lines.

Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via.

Tadatoshi Sekine, Hideki Asai

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits.

Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2010

An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment.

Takanori Uno, Kouji Ichikawa, Yuichi Mabuchi, Atsushi Nakamura, Yuji Okazaki, Hideki Asai

IEICE Trans. Commun., 2010

An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit.

Yuji Okazaki, Takanori Uno, Hideki Asai

IEICE Trans. Electron., 2010

Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation.

Takayuki Watanabe, Hideki Asai

Proceedings of the Design, Automation and Test in Europe, 2010

A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary condition.

Shuichi Aono, Masaki Unno, Hideki Asai

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

CMOS Circuit Simulation Using Latency Insertion Method.

Tadatoshi Sekine, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling.

Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifumi Nishio, Akio Ushida

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane.

Tadatoshi Sekine, Yuichi Tanji, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Acceleration of ADI-FDTD Method by Gauss-Seidel Relaxation Approach.

Yuya Nakazono, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Generating stable and sparse reluctance/inductance matrix under insufficient conditions.

Yuichi Tanji, Takayuki Watanabe, Hideki Asai

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm.

Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Application of Relaxation-Based Technique to ADI-FDTD Method and Its Estimation.

Yuya Nakazono, Hideki Asai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A fast transient simulation based on Model Order Reduction and RLCG-MNA formulation.

Akira Tsuzaki, Toshio Unno, Yuichi Tanji, Hideki Asai

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

An Enhanced Time-Domain Circuit Simulation Technique Based on LIM.

Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation.

Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Fast timing analysis of plane circuits via two-layer CNN-based modeling.

Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifumi Nishio, Akio Ushida

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Large scale RLC circuit analysis using RLCG-MNA formulation.

Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A.

Takafumi Yamamoto, Tsutomu Suzuki, Hideki Asai

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation.

Hiroshi Ninomiya, Kimihiko Numayama, Hideki Asai

Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters.

Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data.

Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Modeling of power distribution networks with signal lines for SPICE simulators.

Takayuki Watanabe, Hideki Asai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits.

Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Optimization procedure of class E amplifiers using SPICE.

Yuichi Tanji, Hiroo Sekiya, Hideki Asai

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Interconnect simulation using FDTD method with variable mesh size technique.

Hirofumi Suzuki, Hidemasa Kubota, Takayuki Watanabe, Hideki Asai

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Generalized method of the time-domain circuit simulation based on LIM with MNA formulation.

Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Three dimensional module packing by simulated annealing.

Hirokazu Yamagishi, Hiroshi Ninomiya, Hideki Asai

Proceedings of the IEEE Congress on Evolutionary Computation, 2005

2004

Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits.

Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai

Proceedings of the 2004 Design, 2004

Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects.

Yuichi Tanji, Hideki Asai

Proceedings of the 41th Design Automation Conference, 2004

2003

Face Image Recognition by 2-Dimensional Discrete Walsh Transform and Multi-Layer Neural Network.

Masahiro Yoshida, Takeshi Kamio, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A Framework for Macromodeling and Mixed-Mode Simulation of Circuits/Interconnects and Electromagnetic Radiations.

Takayuki Watanabe, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values.

Shashidhar Tantry, Yasuyuki Hiraku, Takao Oura, Teru Yoneyama, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Analysis of PCB interconnects using electromagnetic reduction technique.

Takayuki Watanabe, Hideki Asai

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Behavioral modeling of EM devices by selective orthogonal matrix least-squares method.

Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain.

Kenichi Suzuki, Mitsuhiro Takeda, Atsushi Kamo, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally.

Tsutomu Suzuki, Takao Oura, Teru Yoneyama, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values.

Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique.

Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values.

Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique.

Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method.

I. Hattori, Atsushi Kamo, Takayuki Watanabe, Hideki Asai

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A low voltage floating resistor having positive and negative resistance values.

Shashidhar Tantry, Takao Oura, Teru Yoneyama, Hideki Asai

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

A Neuro-Based Optimization Algorithm for Tiling Problems with Rotation.

Shinsuke Manabe, Hideki Asai

Neural Process. Lett., 2001

Two floating resistor circuits and their applications to synaptic weights in analog neural networks.

Shashidhar Tantry, Teru Yoneyama, Hideki Asai

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

High-speed interconnect simulation using MIMO type of adaptive least square method.

Masaya Suzuki, Hirofumi Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Simulation for the optimal placement of decoupling capacitors on printed circuit board.

Atsushi Kamo, Takayuki Watanabe, Hideki Asai

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Neuro-Based Human-Face Recognition with 2-Dimensional Discrete Walsh Transform.

Masahiro Yoshida, Hideki Asai, Takeshi Kamio

Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

Design Method of Limit Cycle Generator by Hysteresis Neural Networks.

Teru Yoneyama, Hideki Asai, Hiroshi Ninomiya

Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

1999

Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method.

Takayuki Watanabe, Hideki Asai

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Expanded GMC for transient analysis of transmission line networks.

Atsushi Kamo, Takayuki Watanabe, Hideki Asai

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Design method of neural networks for limit cycle generator.

Teru Yoneyama, Hiroshi Ninomiya, Hideki Asai

Proceedings of the International Joint Conference Neural Networks, 1999

1998

Transient analysis for high-speed interconnect networks based on AWE and delay evaluation technique.

Takayuki Watanabe, Hideki Asai

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

SPADE : analog/digital mixed signal simulator with analog hardware description language.

Hiroshi Sagesaka, Hisashi Irii, Hideki Asai

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Neural network simulator for spatiotemporal pattern analysis.

Atsushi Kamo, Hiroshi Ninomiya, Teru Yoneyama, Hideki Asai

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997

Application of neuro-based optimization algorithm to three dimensional cylindric puzzles.

Hiroyuki Yamamoto, Takeshi Nakayama, Hiroshi Ninomiya, Hideki Asai

Proceedings of International Conference on Neural Networks (ICNN'97), 1997

1996

Design and implementation of neural network logic circuits with global convergence.

Hiroshi Ninomtya, Kunitaka Egawa, Takeshi Kamio, Hideki Asai

Proceedings of International Conference on Neural Networks (ICNN'96), 1996

Design and implementation of neuro-based discrete Walsh transform processor.

Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai

Proceedings of International Conference on Neural Networks (ICNN'96), 1996

Tiling algorithm with fitting violation function for analog neural array.

Hideki Asai, Takeshi Nakayama, Hiroshi Ninomiya

Proceedings of International Conference on Neural Networks (ICNN'96), 1996

DESIRE3T+: waveform relaxation-based simulator for coupled lossy transmission lines circuits.

Takayuki Watanabe, Hideki Asai

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995

Orthogonalized Steepest Descent Method for Solving Nonlinear Equations.

Hiroshi Ninomiya, Hideki Asai

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Convergence of Hopfield Neural Network for Orthogonal Transformation.

Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Neural network approach to traveling salesman problem based on hierarchical city adjacency.

Hiroshi Ninomiya, Kazumichi Sato, Takeshi Nakayama, Hideki Asai

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

A study of Hopfield neural networks with external noises.

Hideki Asai, Katsuaki Onodera, Takeshi Kamio, Hiroshi Ninomiya

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1994

Relaxation-Based Steady-State Analysis of Single- and Multi-Conductor Transmission Lines in Frequency Domain.

Takeshi Senoo, Hiroaki Makino, Hideki Asai

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective Trace.

Masakatsu Nishigaki, Nobuyuki Tanaka, Hideki Asai

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits.

Masaki Ishida, Koichi Hayashi, Masakatsu Nishigaki, Hideki Asai

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Transient Simulation of Coupled Lossy Interconnects by Window Partitioning Technique.

Vijaya Gopal Bandi, Hideki Asai

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1987

Special parallel processor for lu decomposition of a large-scale sparse matrix.

Hideki Asai, Mitsuo Asai, Mamoru Tanaka

Syst. Comput. Jpn., 1987

1985

Network analysis by hierarchical tearing method.

Hideki Asai, Shinsaku Mori

Syst. Comput. Jpn., 1985