Sherif M. Saif

Orcid: 0000-0002-9014-5590

According to our database1, Sherif M. Saif authored at least 16 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Fog-ROCL: A Fog based RSU Optimum Configuration and Localization in VANETs.
Pervasive Mob. Comput., August, 2023

2022
Hardware Acceleration of Lane Detection Algorithm: A GPU Versus FPGA Comparison.
CoRR, 2022

A UVM-based Verification Approach for MIPI DSI Low-Level Protocol layer.
Proceedings of the International Conference on Microelectronics, 2022

2020
Fog Node Optimum Placement and Configuration Technique for VANETs.
Proceedings of the International Conference on Communications, 2020

Memory Management Approaches in Apache Spark: A Review.
Proceedings of the International Conference on Advanced Intelligent Systems and Informatics, 2020

A Survey of Using Blockchain Aspects in Information Centric Networks.
Proceedings of the International Conference on Advanced Intelligent Systems and Informatics, 2020

2017
Analog layout placement retargeting using Satisfiability Modulo Theories.
Proceedings of the 14th International Conference on Synthesis, 2017

2016
A Platform for Placement of Analog Integrated Circuits Using Satisfiability Modulo Theories.
J. Circuits Syst. Comput., 2016

Pareto front analog layout placement using Satisfiability Modulo Theories.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Analog layout constraints resolution and shape function generation using Satisfiability Modulo Theories.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014
Exploiting satisfiability modulo theories for analog layout automation.
Proceedings of the 9th International Design and Test Symposium, 2014

Multi-device layout templates for nanometer analog design.
Proceedings of the 9th International Design and Test Symposium, 2014

2007
An FPGA implementation of a neural optimization of block truncation coding for image/video compression.
Microprocess. Microsystems, 2007

2006
An FPGA Implementation of a Competitive Hopfield Neural Network for Use in Histogram Equalization.
Proceedings of the International Joint Conference on Neural Networks, 2006

2004
An FPGA implementation of block truncation coding for gray and color images.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003
FPGA implementation of block truncation coding algorithm for gray scale images.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


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