M. Watheq El-Kharashi

According to our database1, M. Watheq El-Kharashi authored at least 92 papers between 2000 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
An ultrafast neural network-based hardware acceleration for nonlinear systems' simulators.
Comput. Electr. Eng., 2019

Parallel Multidimensional Lookahead Sorting Algorithm.
IEEE Access, 2019

Efficient Structured Scan Patterns Retargeting for Hierarchical IEEE 1687 Networks.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Dynamic Power Reduction Methodology based on Reducing Output Transition Rate.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

Reduction of Variations Using Chemometric Model Transfer: A Case Study Using FT-NIR Miniaturized Sensors.
Proceedings of the International Conference on Advanced Machine Learning Technologies and Applications, 2019

2018
Novel Distributed Scheduling Algorithms for mmWave Mesh Networks.
Journal of Circuits, Systems, and Computers, 2018

RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018

A Configurable RISC-V for NoC-Based MPSoCs: A Framework for Hardware Emulation.
Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018

2017
A power-optimized, area-efficient implementation of Connection-Then-Credit NoC physical layer.
Microelectron. J., 2017

Dynamic FPGA Detection and Protection of Hardware Trojan: A Comparative Analysis.
CoRR, 2017

A kernel-based solution for overload in mixed criticality multicore systems.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

WikiTrends: Unstructured Wikipedia-Based Text Analytics Framework.
Proceedings of the Natural Language Processing and Information Systems, 2017

On Error Injection for NoC Platforms: A UVM-based Practical Case Study.
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017

Introducing NoC2: Interconnecting NoC-based Systems through Ethernet.
Proceedings of the 14th International Conference on Mobile Systems and Pervasive Computing (MobiSPC 2017) / 12th International Conference on Future Networks and Communications (FNC 2017) / Affiliated Workshops, 2017

Bloom filter acceleration: A high level synthesis approach.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016
Multi-dimensional analysis of embedded systems security.
Microprocess. Microsystems, 2016

A Platform for Placement of Analog Integrated Circuits Using Satisfiability Modulo Theories.
Journal of Circuits, Systems, and Computers, 2016

Formal Based Methodology for Inferring Memory Mapped Registers.
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

SoC connectivity specification extraction using incomplete RTL design: An approach for Formal connectivity Verification.
Proceedings of the 11th International Design & Test Symposium, 2016

An Enhanced Network-on-chip Simulation for Cluster-based Routing.
Proceedings of the 11th International Conference on Future Networks and Communications (FNC 2016) / The 13th International Conference on Mobile Systems and Pervasive Computing (MobiSPC 2016) / Affiliated Workshops, 2016

Pareto front analog layout placement using Satisfiability Modulo Theories.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

AUTOSAR-based communication coprocessor for automotive ECUs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Design and implementation of BPSK MODEM for IEEE 802.15.4/ZigBee devices.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

ASU: An Experimental Study on Applying Deep Learning in Twitter Named Entity Recognition.
Proceedings of the 2nd Workshop on Noisy User-generated Text, 2016

2015
Process variability-induced NoC link failure: A probabilistic model.
Microelectron. J., 2015

On kernel acceleration of electromagnetic solvers via hardware emulation.
Comput. Electr. Eng., 2015

Embedded Hypervisor Xvisor: A Comparative Analysis.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

On hardware solution of dense linear systems via Gauss-Jordan Elimination.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

SystemVerilog assertion debugging: A visualization and pattern matching model.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

Traffic analysis of multi-core body sensor networks based on Wireless NoC infrastructure.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

Homomorphic Data Isolation for Hardware Trojan Protection.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Finite element emulation-based solver for electromagnetic computations.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Toward the interfacing of systemC-AMS models with hardware-emulated platforms.
Proceedings of the 10th International Design & Test Symposium, 2015

Accelerating electromagnetic simulations: A hardware emulation approach.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A novel scheduling algorithm for mmWave mesh networks using packet aggregation.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Analog layout constraints resolution and shape function generation using Satisfiability Modulo Theories.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Pin-Count and Wire Length Optimization for Electrowetting-on-Dielectric Chips: A Metaheuristics-Based Routing Algorithm.
Proceedings of the Computational Intelligence in Digital and Network Designs and Applications, 2015

2014
Variability-tolerant routing algorithms for Networks-on-Chip.
Microprocess. Microsystems, 2014

Model of a hybrid processor executing C++ with additional quantum functions.
Microprocess. Microsystems, 2014

System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

The Connection-Then-Credit Flow Control Protocol for Networks-On-Chips: Implementation Trade-offs.
Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014

Exploiting satisfiability modulo theories for analog layout automation.
Proceedings of the 9th International Design and Test Symposium, 2014

Power-aware Mapping for 3D-NoC Designs Using Genetic Algorithms.
Proceedings of the 9th International Conference on Future Networks and Communications (FNC'14) / The 11th International Conference on Mobile Systems and Pervasive Computing (MobiSPC'14) / Affiliated Workshops, 2014

E-Voting Attacks and Countermeasures.
Proceedings of the 28th International Conference on Advanced Information Networking and Applications Workshops, 2014

2013
Power consumption of 3D networks-on-chips: Modeling and optimization.
Microprocess. Microsystems, 2013

Unified multi-objective mapping and architecture customisation of networks-on-chip.
IET Computers & Digital Techniques, 2013

An embedded implementation of the Generalized Predictive Control algorithm applied to automotive active suspension systems.
Comput. Electr. Eng., 2013

Authenticated key exchange protocol using neural cryptography with secret boundaries.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

Graph-based approach for software allocation in automotive networked embedded systems: A partition-and-map algorithm.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

Hardware Trojan Protection for Third Party IPs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Variability-tolerant NoC link design.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

2011
Improving Networks-on-Chip performability: A topology-based approach.
I. J. Circuit Theory and Applications, 2011

A reconfigurable, pipelined, conflict directed jumping search SAT solver.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
MPC-On-Chip: An Embedded GPC Coprocessor for Automotive Active Suspension Systems.
Embedded Systems Letters, 2010

Multi-objective optimization of NoC standard architectures using Genetic Algorithms.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2010

Multi-objective optimization for Networks-on-Chip architectures using Genetic Algorithms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Networks-on-chip topology optimization subject to power, delay, and reliability constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A novel conflict directed jumping algorithm for hardware-based SAT solvers.
Proceedings of the 5th International Design and Test Workshop, 2010

2009
Power optimization for application-specific networks-on-chips: A topology-based approach.
Microprocess. Microsystems, 2009

A spam rejection scheme during SMTP sessions based on layer-3 e-mail classification.
J. Netw. Comput. Appl., 2009

Targeting spam control on middleboxes: Spam detection based on layer-3 e-mail content classification.
Comput. Networks, 2009

A Reconfigurable Five-Stage Pipelined SAT Solver.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

2008
Corrections to "Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit" [Dec 07 2683-2695].
IEEE Trans. on Circuits and Systems, 2008

Prioritized e-mail servicing to reduce non-spam delay and loss: A performance analysis.
Int. Journal of Network Management, 2008

Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation.
IET Computers & Digital Techniques, 2008

Design Space Exploration of a Reconfigurable HMAC-Hash Unit.
Journal of Research and Practice in Information Technology, 2008

Power-aware topology optimization for networks-on-chips.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Application-specific networks-on-chip topology customization using network partitioning.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008

TLM-Based Verification of a Combined Switching Networks-on-Chip Router.
Proceedings of the Forum on specification and Design Languages, 2008

Hardware based algorithm for conflict diagnosis in SAT solver.
Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008

2007
Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit.
IEEE Trans. on Circuits and Systems, 2007

Queue Modeling and Implementation for Networks-on-Chip Routers.
Journal of Circuits, Systems, and Computers, 2007

A Platform Approach for Hardware/Software Co-Design with Support for RTOS-Based Systems.
Journal of Circuits, Systems, and Computers, 2007

Modeling and Implementation of an Output-Queuing Router for Networks-on-Chips.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
A hierarchical design methodology for full-search block matching motion estimation.
Multidim. Syst. Sign. Process., 2006

An FPGA implementation of the flexible triangle search algorithm for block based motion estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Binary LNS-based naive Bayes hardware classifier for spam control.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

FPGA-Based SAT Solver.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

Distributed Layer-3 E-Mail Classification for Spam Control.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005
An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Systolic Array-Based String Matching Unit for Spam Blocking.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

An FPGA Design of a Unified Hash Engine for IPSec Authentication.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004
A fast string search algorithm for deep packet classification.
Comput. Commun., 2004

Towards Automating Hardware/Software Co-Design.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

2002
Understanding and implementing computer network protocols through a lab project.
IEEE Trans. Education, 2002

The JAFARDD processor: a Java architecture based on a Folding Algorithm, with Reservation stations, Dynamic translation, and Dual processing.
IEEE Trans. Consumer Electronics, 2002

2001
Adapting Tomasulo's algorithm for bytecode folding based Java processors.
SIGARCH Computer Architecture News, 2001

A robust stack folding approach for Java processors: an operand extraction-based algorithm.
Journal of Systems Architecture, 2001

2000
A quantitative study for Java microprocessor architectural requirements. Part II: high-level language support.
Microprocess. Microsystems, 2000

A quantitative study for Java microprocessor architectural requirements. Part I: Instruction set design.
Microprocess. Microsystems, 2000


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