Mohamed Dessouky
Orcid: 0000-0003-3829-6284
According to our database1,
Mohamed Dessouky
authored at least 101 papers
between 1999 and 2023.
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Bibliography
2023
Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator.
IEEE Access, 2023
Proceedings of the 5th Novel Intelligent and Leading Emerging Sciences Conference, 2023
2022
Design and Implementation of an Improved Variable Step-Size NLMS-Based Algorithm for Acoustic Noise Cancellation.
Circuits Syst. Signal Process., 2022
A General Algorithm for Loop-gain and TDC-resolution Optimization in an ADPLL with a 2-bit TDC Phase detector.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Systematic Design For Multistage Feed-forward Op-amp For High-Speed Continuous-Time ∑Δ ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Direct Digital Frequency Synthesizer Modeling with a Re-configurable DAC Evaluation for Electrochemical Impedance Spectroscopy.
Proceedings of the 2022 IEEE Sensors, Dallas, TX, USA, October 30 - Nov. 2, 2022, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 6.4 GHz Continuous-Time ΣΔ ADC Using Body-Biased Feedforward Op-Amps in 28nm-FDSOI.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Digital ASIC Implementation of RISC-V: OpenLane and Commercial Approaches in Comparison.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
2020
A fabrication of a low-power low-noise neural recording amplifier based on flipped voltage follower.
Microelectron. J., 2020
Proceedings of the 2nd Novel Intelligent and Leading Emerging Sciences Conference, 2020
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Proceedings of the 10th IEEE International Conference on System Engineering and Technology, 2020
2019
Microelectron. J., 2019
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Development of a Generic and a Reconfigurable UVM-Based Verification Environment for SoC Buses.
Proceedings of the 31st International Conference on Microelectronics, 2019
2018
Systematic design and optimization of operational transconductance amplifier using gm/ID design methodology.
Microelectron. J., 2018
Proceedings of the 15th International Conference on Synthesis, 2018
High-Speed 2D Parallel MAC Unit Hardware Accelerator for Convolutional Neural Network.
Proceedings of the Intelligent Systems and Applications, 2018
Proceedings of the 2018 International Conference on Computer and Applications (ICCA), 2018
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018
2017
Comput. Ind. Eng., 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Monte Carlo general sample classification for rare circuit events using Random Forest.
Proceedings of the 14th International Conference on Synthesis, 2017
Power pre-characterized meshing algorithm for finite element thermal analysis of integrated circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
A Platform for Placement of Analog Integrated Circuits Using Satisfiability Modulo Theories.
J. Circuits Syst. Comput., 2016
Proceedings of the 13th International Conference on Synthesis, 2016
Optimization of the output power of a frequency-up conversion piezoelectric energy harvester.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Modeling and analysis of stretching strain in clamped-clamped beams for energy harvesting.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016
Accuracy-improved coupling capacitance model for through-silicon via (TSV) arrays using dimensional analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 11th International Design & Test Symposium, 2016
Regression modeling for subset selection in rare-event statistical circuit simulation.
Proceedings of the 11th International Design & Test Symposium, 2016
A simple model for on-chip microstrip transmission lines in millimeter wave circuits.
Proceedings of the 28th International Conference on Microelectronics, 2016
Optimally matched current mirror layout pattern generation using genetic optimization.
Proceedings of the 28th International Conference on Microelectronics, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015
A low-power, 9-Bit, 1.2 ps resolution two-step time-to-digital converter in 65 nm CMOS.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation.
Proceedings of the 10th International Design & Test Symposium, 2015
Parameterized test patterns methodology for layout design rule checking verification.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
An 8kb SRAM macro in 65nm for ultra-low voltage applications operating from 1.2V to 0.5V.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Analog layout constraints resolution and shape function generation using Satisfiability Modulo Theories.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014
The Connection-Then-Credit Flow Control Protocol for Networks-On-Chips: Implementation Trade-offs.
Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014
Proceedings of the 9th International Design and Test Symposium, 2014
Proceedings of the 9th International Design and Test Symposium, 2014
2013
Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Analysis and design of analog-based voltage controlled oscillator linearization technique.
Proceedings of the 8th International Design and Test Symposium, 2013
A programmable 8-bit, 10MHz BW, 6.8mW, 200MSample/sec, 70dB SNDR VCO-based ADC using SC feedback for VCO linearization.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
2012
Schematic-driven physical verification: Fully automated solution for analog IC design.
Proceedings of the IEEE 25th International SOC Conference, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flow.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A DFM tool for analyzing lithography and stress effects on standard cells and critical path performance in 45nm digital designs.
Proceedings of the 5th International Design and Test Workshop, 2010
2009
Microelectron. J., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008
2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
2004
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
2002
Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio.
Proceedings of the 2002 Design, 2002
2001
Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping.
IEEE J. Solid State Circuits, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 Design, 2000
A 1 V 1 mW digital-audio ΔΣ modulator with 88 dB dynamic range using local switch bootstrapping.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
A current-mode continuous-time Sigma-Delta modulator with delayed return-to-zero feedback.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999