Shigeru Mori

According to our database, Shigeru Mori authored at least 4 papers between 1990 and 1991.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1991

A 45-ns 64-Mb DRAM with a merged match-line test architecture.

Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano

IEEE J. Solid State Circuits, November, 1991

Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond.

Shigeru Kikuda, Hiroshi Miyamoto, Shigeru Mori, Mitsutaka Niiro, Michihiro Yamada

IEEE J. Solid State Circuits, November, 1991

An Address Maskable Parallel Testing for Ultra High Density DRAMs.

Yoshikazu Morooka, Shigeru Mori, Hiroshi Miyamoto, Michihiro Yamada

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM.

Hiroshi Miyamoto, Tadato Yamagata, Shigeru Mori, Tetsuya Aono, Ikuo Ogoh, Michihiro Yamada

IEEE J. Solid State Circuits, April, 1990