Mitsuya Kinoshita

According to our database, Mitsuya Kinoshita authored at least 5 papers between 1991 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2003

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write.

Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto

IEEE J. Solid State Circuits, 2003

A Low Power Embedded DRAM Macro for Battery-Operated LSIs.

Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2001

Design methodology of embedded DRAM with virtual-socket architecture.

Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2001

2000

Design methodology of the embedded DRAM with the virtual socket architecture.

Mitsuya Kinoshita, Tadaaki Yamauchi, Teruhiko Amano, Katsumi Dosaka, Kenshin Arimoto

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1991

A 45-ns 64-Mb DRAM with a merged match-line test architecture.

Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano

IEEE J. Solid State Circuits, November, 1991