Tadato Yamagata

According to our database, Tadato Yamagata authored at least 5 papers between 1995 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1999

A 5.3-GB/s embedded SDRAM core with slight-boost scheme.

Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada

IEEE J. Solid State Circuits, 1999

1997

High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's.

Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada

IEEE J. Solid State Circuits, 1997

1996

A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond.

Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami

IEEE J. Solid State Circuits, 1996

SOI-DRAM circuit technologies for low power high speed multigiga scale memories.

Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto

IEEE J. Solid State Circuits, 1996

1995

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs.

Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto

IEEE J. Solid State Circuits, November, 1995