Shigeto Tanaka

According to our database, Shigeto Tanaka authored at least 3 papers between 2005 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2007

A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture.

Hiroki Sakurai, Shigeto Tanaka, Yasuhiro Sugimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications.

Yasuhiro Sugimoto, Yuji Gohda, Shigeto Tanaka

IEICE Trans. Electron., 2006

2005

The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC.

Shigeto Tanaka, Yuji Gohda, Yasuhiro Sugimoto

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005