Shorin Kyo

According to our database1, Shorin Kyo authored at least 21 papers between 1993 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2013
AutoPilot: message passing parallel programming for a cache incoherent embedded manycore processor.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

2012
Efficient data transfer operations for a SIMD processor array system.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011
IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements.
J. Signal Process. Syst., 2011

Guest Editorial: Special Issue on Computing Architectures for Real-Time Video/Image Analysis.
J. Signal Process. Syst., 2011

A dynamic SIMD/MIMD mode switching processor for embedded real-time image recognition systems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

2009
Mapping schemes of image recognition tasks onto highly parallel SIMD/MIMD processors.
Proceedings of the Third ACM/IEEE International Conference on Distributed Smart Cameras, 2009

IMAPCAR2: A dynamic SIMD/MIMD mode switching processor for embedded systems.
Proceedings of the 2009 IEEE Hot Chips 21 Symposium (HCS), 2009

2008
Overtaking Vehicle Detection Method and Its Implementation Using IMAPCAR Highly Parallel Image Processor.
IEICE Trans. Inf. Syst., 2008

In-vehicle vision processors for driver assistance systems.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
An Integrated Memory Array Processor for Embedded Image Recognition Systems.
IEEE Trans. Computers, 2007

Media Processing LSI Architectures for Automotives - Challenges and Future Trends - .
IEICE Trans. Electron., 2007

A low-cost mixed-mode parallel processor architecture for embedded systems.
Proceedings of the 21th Annual International Conference on Supercomputing, 2007

2005
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004
A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications.
IEICE Trans. Inf. Syst., 2004

2003
A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements.
IEEE J. Solid State Circuits, 2003

2002
A 51.2GOPS Programmable Video Recognition Processor for Vision Based Intelligent Cruise Control Applications.
Proceedings of the IAPR Conference on Machine Vision Applications (IAPR MVA 2002), 2002

2001
IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements.
Proceedings of the 2001 International Conference on Image Processing, 2001

1996
Efficient Implementation of Image Processing Algorithms on Linear Processor Arrays Using the Data Parallel Language IDC.
Proceedings of IAPR Workshop on Machine Vision Applications, 1996

1993
Data Stream Control Optimization in Dataflow Architectures.
Proceedings of the 7th international conference on Supercomputing, 1993

Dataflow Graph Optimization for Dataflow Architectures - A Dataflow Optimizing Compiler.
Proceedings of the 1993 International Conference on Parallel Processing, 1993


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