Shin'ichiro Okazaki
According to our database1,
Shin'ichiro Okazaki
authored at least 25 papers
between 1992 and 2012.
Collaborative distances:
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Bibliography
2012
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012
2011
IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements.
J. Signal Process. Syst., 2011
A dynamic SIMD/MIMD mode switching processor for embedded real-time image recognition systems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application.
IPSJ Trans. Syst. LSI Des. Methodol., 2010
2009
Mapping schemes of image recognition tasks onto highly parallel SIMD/MIMD processors.
Proceedings of the Third ACM/IEEE International Conference on Distributed Smart Cameras, 2009
Proceedings of the 2009 IEEE Hot Chips 21 Symposium (HCS), 2009
2008
Overtaking Vehicle Detection Method and Its Implementation Using IMAPCAR Highly Parallel Image Processor.
IEICE Trans. Inf. Syst., 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEEE Trans. Computers, 2007
Proceedings of the 21th Annual International Conference on Supercomputing, 2007
2005
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005
2004
A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications.
IEICE Trans. Inf. Syst., 2004
2003
A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements.
IEEE J. Solid State Circuits, 2003
2001
Proceedings of the 2001 International Conference on Image Processing, 2001
1996
IMAP-VISION: An SIMD Processor with High-Speed On-chip Memory and Large Capacity External Memory.
Proceedings of IAPR Workshop on Machine Vision Applications, 1996
An integrated memory array processor with a synchronous-DRAM interface for real-time vision applications.
Proceedings of the 13th International Conference on Pattern Recognition, 1996
1995
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications.
IEEE J. Solid State Circuits, June, 1995
A compact real-time vision system using integrated memory array processor architecture.
IEEE Trans. Circuits Syst. Video Technol., 1995
1994
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM.
IEEE J. Solid State Circuits, November, 1994
Mach. Vis. Appl., 1994
Proceedings of IAPR Workshop on Machine Vision Applications, 1994
1993
Dataflow Graph Optimization for Dataflow Architectures - A Dataflow Optimizing Compiler.
Proceedings of the 1993 International Conference on Parallel Processing, 1993
1992
Proceedings of IAPR Workshop on Machine Vision Applications, 1992