Shwetabh Verma

According to our database1, Shwetabh Verma authored at least 7 papers between 2003 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2013
A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications.
IEEE J. Solid State Circuits, 2013

A 10.3GS/s 6b flash ADC for 10G Ethernet applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2006
An integrated VCSEL driver for 10Gb ethernet in 0.13µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A 17-mW 0.66-mm<sup>2</sup> direct-conversion receiver for 1-Mb/s cable replacement.
IEEE J. Solid State Circuits, 2005

2004
A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis.
IEEE J. Solid State Circuits, 2004

2003
A unified model for injection-locked frequency dividers.
IEEE J. Solid State Circuits, 2003


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