Thomas H. Lee

According to our database1, Thomas H. Lee authored at least 69 papers between 1996 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Analysis and Design of a Tetrahedral Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Hybrid Analysis and Simulation Methodology for Noise in Active Mixers.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2021
Hybrid Frequency Domain Simulation Method to Speed-up Analysis of Injection Locked Oscillators.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

SE3: Favorite Circuit Design and Testing Mistakes of Starting Engineers.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Modeling of Injection Locking in Neurons for Neuromorphic and Biomedical Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A Simple Linear Time-Variant Theory of Superregeneration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018
A 125 pJ/hit 5 mW 28 GHz Superregenerative Receiver with Automatic Gain Control and Energy Efficient Startup for Burst Mode IoE Applications.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2015
A Phase-Interpolation and Quadrature-Generation Method Using Parametric Energy Transfer in CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014
A 0.96mW, 5.3-6.75GHz, phase-interpolation and quadrature-generation method using parametric energy transfer in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Terahertz electronics: The last frontier.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2010
Circuit-Based Characterization of Device Noise Using Phase Noise Data.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
A 10Gb/s NRZ receiver with feedforward equalizer and glitch-free phase-frequency detector.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 3MHz Low-Voltage Buck Converter with Improved Light Load Efficiency.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Circuit-Based Noise Parameter Extraction Technique for MOSFETs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 10Gb/s Equalizer with Decision Feedback for High Speed Serial Links.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Comment on Corrections to "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier".
IEEE J. Solid State Circuits, 2006

Ordered and chaotic electrical solitons: communication perspectives.
IEEE Commun. Mag., 2006

3D on-chip networking technology based on post-silicon devices for future networks-on-chip.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

2005
An analytical formulation of phase noise of signals with Gaussian-distributed jitter.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

A 17-mW 0.66-mm<sup>2</sup> direct-conversion receiver for 1-Mb/s cable replacement.
IEEE J. Solid State Circuits, 2005

Corrections to "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier".
IEEE J. Solid State Circuits, 2005

Minimum achievable phase noise of RC oscillators.
IEEE J. Solid State Circuits, 2005

2004
A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis.
IEEE J. Solid State Circuits, 2004

2003
A unified model for injection-locked frequency dividers.
IEEE J. Solid State Circuits, 2003

512-Mb PROM with a three-dimensional array of diode/antifuse memory cells.
IEEE J. Solid State Circuits, 2003

Automatic phase alignment for a fully integrated Cartesian feedback power amplifier system.
IEEE J. Solid State Circuits, 2003

Lumped, inductorless oscillators: how far can they go? [phase noise reduction limit].
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

Optimization of phase-locked loop circuits via geometric programming.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design".
IEEE J. Solid State Circuits, 2002

A noise optimization technique for integrated low-noise amplifiers.
IEEE J. Solid State Circuits, 2002

Research Paper: Clinician Use of a Palmtop Drug Reference Guide.
J. Am. Medical Informatics Assoc., 2002

Viewpoint: Integrating Medical Informatics and Health Services Research: The Need for Dual Training at the Clinical Health Systems and Policy Levels.
J. Am. Medical Informatics Assoc., 2002

2001
Optimal design of a CMOS op-amp via geometric programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver.
IEEE J. Solid State Circuits, 2001

Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design.
IEEE J. Solid State Circuits, 2001

2000
CMOS RF integrated circuits at 5 GHz and beyond.
Proc. IEEE, 2000

Comments on "Design issues in CMOS differential LC oscillators" [and reply].
IEEE J. Solid State Circuits, 2000

A 5-GHz CMOS wireless LAN receiver front end.
IEEE J. Solid State Circuits, 2000

A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver.
IEEE J. Solid State Circuits, 2000

Bandwidth extension in CMOS with optimized on-chip inductors.
IEEE J. Solid State Circuits, 2000

Oscillator phase noise: a tutorial.
IEEE J. Solid State Circuits, 2000

A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver.
IEEE J. Solid State Circuits, 2000

Survey of Physicians' Experience Using a Handheld Drug Reference Guide.
Proceedings of the AMIA 2000, 2000

1999
RF Passive IC Components.
Proceedings of the VLSI Handbook., 1999

Superharmonic injection-locked frequency dividers.
IEEE J. Solid State Circuits, 1999

Simple accurate expressions for planar spiral inductances.
IEEE J. Solid State Circuits, 1999

Jitter and phase noise in ring oscillators.
IEEE J. Solid State Circuits, 1999

Design issues in CMOS differential LC oscillators.
IEEE J. Solid State Circuits, 1999

A portable digital DLL for high-speed CMOS interface circuits.
IEEE J. Solid State Circuits, 1999

A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter.
IEEE J. Solid State Circuits, 1999

Design and optimization of LC oscillators.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Optimization of Inductor Circuits via Geometric Programming.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Low-power dividerless frequency synthesis using aperture phase detection.
IEEE J. Solid State Circuits, 1998

A 115-mW, 0.5-μm CMOS GPS receiver with wide dynamic-range active filters.
IEEE J. Solid State Circuits, 1998

Fractal capacitors.
IEEE J. Solid State Circuits, 1998

Corrections to "A General Theory of Phase Noise in Electrical Oscillators".
IEEE J. Solid State Circuits, 1998

A general theory of phase noise in electrical oscillators.
IEEE J. Solid State Circuits, 1998

CMOS VCOs for frequency synthesis in wireless biotelemetry.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Automated design of folded-cascode op-amps with sensitivity analysis.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

GPCAD: a tool for CMOS op-amp synthesis.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
A 12-mW wide dynamic range CMOS front-end for a portable GPS receiver.
IEEE J. Solid State Circuits, 1997

A 1.5-V, 1.5-GHz CMOS low noise amplifier.
IEEE J. Solid State Circuits, 1997

1996
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor.
IEEE J. Solid State Circuits, 1996


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