Dean Liu

Orcid: 0009-0006-3465-6026

According to our database1, Dean Liu authored at least 12 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology.
IEEE J. Solid State Circuits, January, 2024

2023
A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2013
A 10.3GS/s 6b flash ADC for 10G Ethernet applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2006
An integrated VCSEL driver for 10Gb ethernet in 0.13µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2005

2003
A Framework for Designing Reusable Analog Circuits.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops.
IEEE J. Solid State Circuits, 2002

Analysis of Blocking Dynamic Circuits.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Macro-modeling concepts for the chip electrical interface.
Proceedings of the 39th Design Automation Conference, 2002

2001
IC Power Distribution Challenges.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000
A variable-frequency parallel I/O interface with adaptive power-supply regulation.
IEEE J. Solid State Circuits, 2000

1999
Timing analysis including clock skew.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999


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