Siarhei S. Zalivaka

According to our database, Siarhei S. Zalivaka authored at least 6 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response.

Siarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang

IEEE Trans. Inf. Forensics Secur., 2019

2017

FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability.

Siarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Low-cost fortification of arbiter PUF against modeling attack.

Siarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Multi-valued Arbiters for quality enhancement of PUF responses on FPGA implementation.

Siarhei S. Zalivaka, Alexander V. Puchkov, Vladimir P. Klybik, Alexander A. Ivaniuk, Chip-Hong Chang

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication.

Yuan Cao, Le Zhang, Siarhei S. Zalivaka, Chip-Hong Chang, Shoushun Chen

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014

CMOS image sensor based physical unclonable function for smart phone security applications.

Yuan Cao, Siarhei S. Zalivaka, Le Zhang, Chip-Hong Chang, Shoushun Chen

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014