Chip-Hong Chang
Orcid: 0000-0002-8897-6176Affiliations:
- Nanyang Technological University, Singapore (PhD 1998)
According to our database1,
Chip-Hong Chang
authored at least 264 papers
between 1993 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2018, "For contributions to hardware security".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on scopus.com
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on publons.com
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on orcid.org
On csauthors.net:
Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
2023
An Imperceptible Data Augmentation Based Blackbox Clean-Label Backdoor Attack on Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Guest Editorial Special Issue on the Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022).
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
PUF-Based Mutual Authentication and Key Exchange Protocol for Peer-to-Peer IoT Applications.
IEEE Trans. Dependable Secur. Comput., 2023
Defense against ML-based Power Side-channel Attacks on DNN Accelerators with Adversarial Attacks.
CoRR, 2023
CoRR, 2023
A Lightweight PUF-based Secure Group Key Agreement Protocol for Wireless Sensor Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
White-Box Adversarial Attacks on Deep Learning-Based Radio Frequency Fingerprint Identification.
Proceedings of the IEEE International Conference on Communications, 2023
MERCURY: An Automated Remote Side-channel Attack to Nvidia Deep Learning Accelerator.
Proceedings of the International Conference on Field Programmable Technology, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023
An Empirical Study of the Inherent Resistance of Knowledge Distillation Based Federated Learning to Targeted Poisoning Attacks.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
Proceedings of the Findings of the Association for Computational Linguistics: ACL 2023, 2023
2022
A DNN Fingerprint for Non-Repudiable Model Ownership Identification and Piracy Detection.
IEEE Trans. Inf. Forensics Secur., 2022
A New Energy-Efficient and High Throughput Two-Phase Multi-Bit per Cycle Ring Oscillator-Based True Random Number Generator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Area, Time and Energy Efficient Multicore Hardware Accelerators for Extended Merkle Signature Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Radio Frequency Fingerprints vs. Physical Unclonable Functions - Are They Twins, Competitors, or Allies?
IEEE Netw., 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
A Practical Man-in-the-Middle Attack on Deep Learning Edge Device by Sparse Light Strip Injection into Camera Data Lane.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A Buyer-traceable DNN Model IP Protection Method Against Piracy and Misappropriation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Stealthy and Robust Glitch Injection Attack on Deep Learning Accelerator for Target With Variational Viewpoint.
IEEE Trans. Inf. Forensics Secur., 2021
IEEE Trans. Inf. Forensics Secur., 2021
A New PUF Based Lock and Key Solution for Secure In-Field Testing of Cryptographic Chips.
IEEE Trans. Emerg. Top. Comput., 2021
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs.
J. Cryptogr. Eng., 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Secure Mutual Authentication and Key-Exchange Protocol between PUF-Embedded IoT Endpoints.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Live Demonstration: Event-Driven Physical Unclonable Function for Proactive Monitoring System by Dynamic Vision Sensor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Forward Error Compensation Approach for Fault Resilient Deep Neural Network Accelerator Design.
Proceedings of the ASHES@CCS 2021: Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security, 2021
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021
2020
A 1036-F<sup>2</sup>/Bit High Reliability Temperature Compensated Cross-Coupled Comparator-Based PUF.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A New Polarization Image Demosaicking Algorithm by Exploiting Inter-Channel Correlations With Guided Filtering.
IEEE Trans. Image Process., 2020
Ed-PUF: Event-Driven Physical Unclonable Function for Camera Authentication in Reactive Monitoring System.
IEEE Trans. Inf. Forensics Secur., 2020
A PUF-Based Data-Device Hash for Tampered Image Detection and Source Camera Identification.
IEEE Trans. Inf. Forensics Secur., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Reducing Temperature Induced Unreliability in Sub-Threshold Strong PUFs through Circuit Modeling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Imperceptible Misclassification Attack on Deep Learning Accelerator by Glitch Injection.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the CCS '20: 2020 ACM SIGSAC Conference on Computer and Communications Security, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response.
IEEE Trans. Inf. Forensics Secur., 2019
UDhashing: Physical Unclonable Function-Based User-Device Hash for Endpoint Authentication.
IEEE Trans. Ind. Electron., 2019
IEEE Trans. Dependable Secur. Comput., 2019
Area- and Power-Efficient Nearly-Linear Phase Response IIR Filter by Iterative Convex Optimization.
IEEE Access, 2019
An Energy-Efficient Current-Starved Inverter Based Strong Physical Unclonable Function With Enhanced Temperature Stability.
IEEE Access, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
An In-Pixel Gain Amplifier Based Event-Driven Physical Unclonable Function for CMOS Dynamic Vision Sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
High-Speed True Random Number Generator Based on Differential Current Starved Ring Oscillators with Improved Thermal Stability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Analysis of Circuit Aging on Accuracy Degradation of Deep Neural Network Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019
Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, 2019
Detecting Adversarial Examples for Deep Neural Networks via Layer Directed Discriminative Noise Injection.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
Vulnerability Analysis on Noise-Injection Based Hardware Attack on Deep Neural Networks.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
A Modeling Attack Resistant Deception Technique for Securing PUF based Authentication.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
2018
A New Accurate and Fast Homography Computation Algorithm for Sports and Traffic Video Analysis.
IEEE Trans. Circuits Syst. Video Technol., 2018
Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Low Power Diode-Clamped Inverter-Based Strong Physical Unclonable Function for Robust and Lightweight Authentication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Active IC Metering of Digital Signal Processing Subsystem with Two-Tier Activation for Secure Split Test.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Sub-pico Joules Per Bit Robust Physical Unclonable Function Based on Subthreshold Voltage References.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Current Comparator Based Physical Unclonable Function with High Reliability and Energy Efficiency.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Towards Ideal Lattice-Based Cryptography on ASIC: A Custom Implementation of Number Theoretic Transform.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Facial biohashing based user-device physical unclonable function for bring your own device security.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
A Fully Digital Physical Unclonable Function Based Temperature Sensor for Secure Remote Sensing.
Proceedings of the 27th International Conference on Computer Communication and Networks, 2018
Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018
2017
A Scaling-Assisted Signed Integer Comparator for the Balanced Five-Moduli Set RNS 2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+ 1, 2<sup>n+1</sup>-1, 2<sup>n-1</sup>-1.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Static and Dynamic Obfuscations of Scan Data Against Scan-Based Side-Channel Attacks.
IEEE Trans. Inf. Forensics Secur., 2017
ACRO-PUF: A Low-power, Reliable and Aging-Resilient Current Starved Inverter-Based Ring Oscillator Physical Unclonable Function.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
New Algorithm for Signed Integer Comparison in {2<sup>n+k</sup>, 2<sup>n</sup>-1, 2<sup>n</sup>+1, 2<sup>n±1</sup>-1} and Its Efficient Hardware Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Current mirror array: A novel lightweight strong PUF topology with enhanced reliability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A new write-contention based dual-port SRAM PUF with multiple response bits per cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017
An energy-efficient true random number generator based on current starved ring oscillators.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Erratum to "Efficient VLSI Implementation of 2<sup>n</sup> Scaling of Signed Integer in RNS {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1}".
IEEE Trans. Very Large Scale Integr. Syst., 2016
A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1}.
IEEE Trans. Very Large Scale Integr. Syst., 2016
DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory.
IEEE Trans. Inf. Forensics Secur., 2016
Hypergraph Based Minimum Arborescence Algorithm for the Optimization and Reoptimization of Multiple Constant Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
A Non-Iterative Multiple Residue Digit Error Detection and Correction Algorithm in RRNS.
IEEE Trans. Computers, 2016
Proceedings of the International SoC Design Conference, 2016
A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A new event-driven Dynamic Vision Sensor based Physical Unclonable Function for camera authentication in reactive monitoring system.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
Multi-valued Arbiters for quality enhancement of PUF responses on FPGA implementation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Low-power, lightweight and reliability-enhanced current starved inverter based RO PUFs.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
Accelerating residue-to-binary conversion of very high cardinality moduli set for fully homomorphic encryption.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell.
IEEE Trans. Inf. Forensics Secur., 2015
Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Computers, 2015
Statistical analysis and design of 6T SRAM cell for physical unclonable function with dual application modes.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
A high-speed and area-efficient sign detector for three moduli set RNS {2n, 2n-1, 2n+1}.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
Exploiting Process Variations and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions.
IEEE Trans. Inf. Forensics Secur., 2014
IEEE Trans. Inf. Forensics Secur., 2014
A Cluster-Based Distributed Active Current Sensing Circuit for Hardware Trojan Detection.
IEEE Trans. Inf. Forensics Secur., 2014
A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
A 0.7 V low-power fully programmable Gaussian function generator for brain-inspired Gaussian correlation associative memory.
Neurocomputing, 2014
A modular design of elliptic-curve point multiplication for resource constrained devices.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
CMOS image sensor based physical unclonable function for smart phone security applications.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A new algorithm for single residue digit error correction in Redundant Residue Number System.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Design of programmable FIR filters using Canonical Double Based Number Representation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Area-efficient and fast sign detection for four-moduli set RNS {2<sup>n</sup> -1, 2<sup>n</sup>, 2<sup>n</sup> +1, 22<sup>n</sup> +1}.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Leakage-resilient memory-based physical unclonable function using phase change material.
Proceedings of the International Carnahan Conference on Security Technology, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
New algorithm for signed integer comparison in four-moduli superset {2<sup>n</sup>, 2<sup>n</sup> -1, 2<sup>n</sup> +1, 2<sup>n+1</sup>-1}.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits.
Integr., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A signed integer programmable power-of-two scaler for {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1} RNS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Area-Power Efficient Modulo 2<sup>n</sup>-1 and Modulo 2<sup>n</sup>+1 Multipliers for {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1} Based RNS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
A VLSI Efficient Programmable Power-of-Two Scaler for 2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1 RNS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Dynamical Systems Guided Design and Analysis of Silicon Oscillators for Central Pattern Generators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011).
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
State encoding watermarking for field authentication of sequential circuit intellectual property.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A fast and compact circuit for integer square root computation based on Mitchell logarithmic method.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
A unified {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1} RNS scaler with dual scaling constants.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
A post-processing scan-chain watermarking scheme for VLSI intellectual property protection.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Bayesian Separation With Sparsity Promotion in Perceptual Wavelet Domain for Speech Enhancement and Hybrid Speech Recognition.
IEEE Trans. Syst. Man Cybern. Part A, 2011
Radix-8 Booth Encoded Modulo 2 <sup>n</sup> -1 Multipliers With Adaptive Delay for High Dynamic Range Residue Number System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Sign-Extension Avoidance and Word-Length Optimization by Positive-Offset Representation for FIR Filter Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set 2<sup>n</sup> - 1, 2<sup>n</sup>, 2<sup>n</sup> + 1.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling.
J. Low Power Electron., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
On "A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Fast hard multiple generators for radix-8 Booth encoded modulo 2<sup>n</sup>-1 and modulo 2<sup>n</sup>+1 multipliers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A novel counter-based low complexity inner-product architecture for high speed inputs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Real-time thermal management of 3D multi-core system with fine-grained cooling control.
Proceedings of the IEEE International Conference on 3D System Integration, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Fixed and Variable Multi-modulus Squarer Architectures for Triple Moduli base of RNS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Optimization of Structural Adders in Fixed Coefficient Transposed Direct Form FIR Filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Contention Resolution - A New Approach to Versatile Subexpressions Sharing in Multiple Constant Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2<sup>m</sup>).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Intellectual property authentication by watermarking scan chain in design-for-testability flow.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
A Generalized Time-Frequency Subtraction Method for Robust Speech Enhancement Based on Wavelet Filter Banks Modeling of Human Auditory System.
IEEE Trans. Syst. Man Cybern. Part B, 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Low-power differential coefficients-based FIR filters using hardware-optimised multipliers.
IET Circuits Devices Syst., 2007
Hamming weight pyramid - A new insight into canonical signed digit representation and its applications.
Comput. Electr. Eng., 2007
Watermarking for IP Protection through Template Substitution at Logic Synthesis Level.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Improved differential coefficients-based low power FIR filters. Part I. Fundamentals.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A Kalman filter based on wavelet filter-bank and psychoacoustic modeling for speech enhancement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A fast kernel for unifying GF(p) and GF(2<sup>m</sup>) Montgomery multiplications in a scalable pipelined architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Maximum likelihood disjunctive decomposition to reduced multirooted DAG for FIR filter design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Syst. Man Cybern. Part B, 2005
IEEE Trans. Neural Networks, 2005
IEEE Trans. Circuits Syst. Video Technol., 2005
Contention resolution algorithm for common subexpression elimination in digital filter design.
IEEE Trans. Circuits Syst. II Express Briefs, 2005
J. Circuits Syst. Comput., 2005
I<sup>2</sup>CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
2004
Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
A new contention resolution algorithm for the design of minimal logic depth multiplierless filters.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
HWP: a new insight into canonical signed digit.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Self-organizing topological tree.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Frequency sensitive self-organizing maps and its application in color quantization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Design of residue-to-binary converter for a new 5-moduli superset residue number system.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Performance Evaluation of Direct Form FIR Filter with Merged Arithmetic Architecture.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
FPGA implementation of a frequency adaptive learning SOFM for digital color still imaging.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Design of a high speed reverse converter for a new 4-moduli set residue number system.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
New efficient residue-to-binary converters for 4-moduli set {2<sup>n</sup> - 1, 2<sup>n</sup>, 2<sup>n</sup> + 1, 2<sup>n+1</sup> - 1}.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
An adaptive initialization technique for color quantization by self organizing feature map.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
2002
Boolean Matching Filters Based on Row and Column Weights of Reed-Muller Polarity Coefficient Matrix.
VLSI Design, 2002
Field programable gate array based architecture for real time image segmentation by region growing algorithm.
J. Electronic Imaging, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
On the Initialization and Training Methods for Kohonen Self-Organizing Feature Maps in Color Image Quantization.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2000
VLSI Design, 2000
1999
An Efficient Algorithm for the Calculation of Generalized Adding and Arithmetic Transforms From Disjoint Cubes of Boolean Functions.
VLSI Design, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
Spherical Harmonic Modeling of a 0.05 μm Base BJT: A Comparison with Monte Carlo and Asymptotic Analysis.
VLSI Design, 1998
1997
Forward and Inverse Transformations Between Haar Spectra and Ordered Binary Decision Diagrams of Boolean Functions.
IEEE Trans. Computers, 1997
1995
Generation of Multi-Polarity Arithmetic Transform from Reduced Representation of Boolean Functions.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
Efficient Algorithms for the Calculation of Arithmetic Spectrum from OBDD & Synthesis of OBDD from Arithmetic Spectrum for Incompletely Specified Boolean Functions.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
J. Intell. Transp. Syst., 1993