Silvio Misera

According to our database, Silvio Misera authored at least 6 papers between 2004 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

Simulated fault injections and their acceleration in SystemC.

Silvio Misera, Heinrich Theodor Vierhaus, André Sieber

Microprocess. Microsystems, 2008

2007

Hardwarenahe Fehlersimulation mit effektiven SystemC-Modellen.

Silvio Misera, André Sieber

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Timing- / Power-Optimization for Digital Logic Based on Standard Cells.

Heinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Fault Injection Techniques and their Accelerated Simulation in SystemC.

Silvio Misera, Heinrich Theodor Vierhaus, André Sieber

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

A Mixed Language Fault Simulation of VHDL and SystemC.

Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2004

FIT - A Parallel Hierarchical Fault Simulation Environment.

Silvio Misera, Heinrich Theodor Vierhaus

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004