Somayyeh Koohi
Orcid: 0000-0002-3105-2511
  According to our database1,
  Somayyeh Koohi
  authored at least 36 papers
  between 2007 and 2025.
  
  
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
  2025
Pip-SW: Pipeline Architectures for Accelerating Smith-Waterman Algorithm on FPGA Platforms.
    
  
    IEEE Trans. Emerg. Top. Comput., 2025
    
  
  2024
    CoRR, 2024
    
  
  2023
BiComp-DTA: Drug-target binding affinity prediction through complementary biological-related and compression-based featurization approach.
    
  
    PLoS Comput. Biol., March, 2023
    
  
Flat Ball: Dynamic topology for energy management of optical interconnection networks in data centers.
    
  
    Opt. Switch. Netw., March, 2023
    
  
An automated ultra-fast, memory-efficient, and accurate method for viral genome classification.
    
  
    J. Biomed. Informatics, March, 2023
    
  
An Assessment of PC-mer's Performance in Alignment-Free Phylogenetic Tree Construction.
    
  
    CoRR, 2023
    
  
  2022
HFOS<sub>L</sub>: hyper scale fast optical switch-based data center network with L-level sub-network.
    
  
    Telecommun. Syst., 2022
    
  
  2021
Free-Space Optical Neural Network Based on Optical Nonlinearity and Pooling Operations.
    
  
    IEEE Access, 2021
    
  
  2019
OMUX: Optical Multicast and Unicast-capable interconnection network for data centers.
    
  
    Opt. Switch. Netw., 2019
    
  
    Nano Commun. Networks, 2019
    
  
  2018
    Proceedings of the 26th Euromicro International Conference on Parallel, 2018
    
  
    Proceedings of the 21st Conference on Innovation in Clouds, 2018
    
  
  2017
    J. Parallel Distributed Comput., 2017
    
  
  2016
    Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
    
  
  2015
    Comput. Electr. Eng., 2015
    
  
  2014
    ACM Trans. Embed. Comput. Syst., 2014
    
  
    IEEE Trans. Computers, 2014
    
  
  2012
    J. Parallel Distributed Comput., 2012
    
  
    Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
    
  
  2011
GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses.
    
  
    Microprocess. Microsystems, 2011
    
  
Hierarchical opto-electrical on-chip network for future multiprocessor architectures.
    
  
    J. Syst. Archit., 2011
    
  
    Proceedings of the NOCS 2011, 2011
    
  
Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures.
    
  
    Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
    
  
An Optical Wavelength Switching Architecture for a High-Performance Low-Power Photonic NoC.
    
  
    Proceedings of the 25th IEEE International Conference on Advanced Information Networking and Applications Workshops, 2011
    
  
  2010
    Proceedings of the 18th Euromicro Conference on Parallel, 2010
    
  
Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability.
    
  
    Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
    
  
  2009
    Proceedings of the Third International Symposium on Networks-on-Chips, 2009
    
  
  2008
High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs.
    
  
    Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
    
  
A Novel Partitioned Encoding Scheme for Reducing Total Power Consumption of Parallel Bus.
    
  
    Proceedings of the Advances in Computer Science and Engineering, 2008
    
  
    Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008
    
  
  2007
    Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007
    
  
An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models.
    
  
    Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
    
  
Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs.
    
  
    Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007