Massoud Pedram
Orcid: 0000-0002-2677-7307Affiliations:
- University of Southern California, Los Angeles, USA
According to our database1,
Massoud Pedram
authored at least 736 papers
between 1988 and 2024.
Collaborative distances:
Collaborative distances:
Awards
ACM Fellow
ACM Fellow 2023, "For contributions to low power design of VLSI circuits and to energy efficient computing".
IEEE Fellow
IEEE Fellow 2001, "For contributions to the theory and practice of low-power design and CAD.".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on zbmath.org
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on orcid.org
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on id.loc.gov
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on isni.org
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on dl.acm.org
On csauthors.net:
Bibliography
2024
A High-Performance, Conflict-Free Memory-Access Architecture for Modular Polynomial Multiplication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
Scalable Superconductor Neuron with Ternary Synaptic Connections for Ultra-Fast SNN Hardware.
CoRR, 2024
Memory-Efficient Vision Transformers: An Activation-Aware Mixed-Rank Compression Strategy.
CoRR, 2024
2023
A<sup>2</sup>P-MANN: Adaptive Attention Inference Hops Pruned Memory-Augmented Neural Networks.
IEEE Trans. Neural Networks Learn. Syst., November, 2023
ACM Trans. Design Autom. Electr. Syst., July, 2023
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis.
ACM Trans. Reconfigurable Technol. Syst., June, 2023
X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory Units.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
Federated learning by employing knowledge distillation on edge devices with limited hardware resources.
Neurocomputing, April, 2023
ACM Trans. Design Autom. Electr. Syst., January, 2023
Efficient Error Estimation for High-Level Design Space Exploration of Approximate Computing Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2023
IEEE Trans. Computers, 2023
IACR Cryptol. ePrint Arch., 2023
CoRR, 2023
CoRR, 2023
CoRR, 2023
Sensitivity-Aware Mixed-Precision Quantization and Width Optimization of Deep Neural Networks Through Cluster-Based Tree-Structured Parzen Estimation.
CoRR, 2023
A Life-Cycle Energy and Inventory Analysis of Adiabatic Quantum-Flux-Parametron Circuits.
CoRR, 2023
CoRR, 2023
BlendNet: Design and Optimization of a Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions.
CoRR, 2023
SNT: Sharpness-Minimizing Network Transformation for Fast Compression-friendly Pretraining.
CoRR, 2023
FLOAT: Fast Learnable Once-for-All Adversarial Training for Tunable Trade-off between Accuracy and Robustness.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023
Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
Toward Adversary-aware Non-iterative Model Pruning through Dynamic Network Rewiring of DNNs.
ACM Trans. Embed. Comput. Syst., September, 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
An Adaptive Memory-Side Encryption Method for Improving Security and Lifetime of PCM-Based Main Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Computers, 2022
Neurocomputing, 2022
IEEE Des. Test, 2022
Have your QEC and Bandwidth too!: A lightweight cryogenic decoder for common / trivial errors, and efficient bandwidth + execution management otherwise.
CoRR, 2022
A Fast and Efficient Conditional Learning for Tunable Trade-Off between Accuracy and Robustness.
CoRR, 2022
An Efficient Error Estimation Technique for Pruning Approximate Data-Flow Graphs in Design Space Exploration.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
X-NVDLA: Runtime Accuracy Configurable NVDLA based on Employing Voltage Overscaling Approach.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
BMPQ: Bit-Gradient Sensitivity-Driven Mixed-Precision Quantization of DNNs from Scratch.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the Approximate Computing, 2022
2021
OPTIMA: An Approach for Online Management of Cache Approximation Levels in Approximate Processing Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2021
An Energy-Efficient Inference Method in Convolutional Neural Networks Based on Dynamic Adjustment of the Pruning Level.
ACM Trans. Design Autom. Electr. Syst., 2021
A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits.
ACM Trans. Design Autom. Electr. Syst., 2021
JointDNN: An Efficient Training and Inference Engine for Intelligent Mobile Cloud Computing Services.
IEEE Trans. Mob. Comput., 2021
LATIM: Loading-Aware Offline Training Method for Inverter-Based Memristive Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Reliability Enhancement of Inverter-Based Memristor Crossbar Neural Networks Using Mathematical Analysis of Circuit Non-Idealities.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Mach. Vis. Appl., 2021
IEEE Internet Things J., 2021
CoRR, 2021
CoRR, 2021
CoRR, 2021
Spike-Thrift: Towards Energy-Efficient Deep Spiking Neural Networks by Limiting Spiking Activity via Attention-Guided Compression.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2021
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
HIRE-SNN: Harnessing the Inherent Robustness of Energy-Efficient Deep Spiking Neural Networks by Training with Crafted Input Noise.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
qSeq: Full Algorithmic and Tool Support for Synthesizing Sequential Circuits in Superconducting SFQ Technology.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Interstice: Inverter-Based Memristive Neural Networks Discretization for Function Approximation Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020
RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Design Exploration of Energy-Efficient Accuracy-Configurable Dadda Multipliers With Improved Lifetime Based on Voltage Overscaling.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Energy-aware Scheduling of Task Graphs with Imprecise Computations and End-to-end Deadlines.
ACM Trans. Design Autom. Electr. Syst., 2020
Offline Training Improvement of Inverter-Based Memristive Neural Networks Using Inverter Voltage Characteristic Smoothing.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
O⁴-DNN: A Hybrid DSP-LUT-Based Processing Unit With Operation Packing and Out-of-Order Execution for Efficient Realization of Convolutional Neural Networks on FPGA Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Computers, 2020
Circuit-Level Techniques for Logic and Memory Blocks in Approximate Computing Systemsx.
Proc. IEEE, 2020
Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2020
CoRR, 2020
EGAN: A Framework for Exploring the Accuracy vs. Energy Efficiency Trade-off in Hardware Implementation of Error Resilient Applications.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Energy-aware Scheduling of Jobs in Heterogeneous Cluster Systems Using Deep Reinforcement Learning.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Low-power Accuracy-configurable Carry Look-ahead Adder Based on Voltage Overscaling Technique.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Efficient Training of Deep Convolutional Neural Networks by Augmentation in Embedding Space.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Deep-PowerX: a deep learning-based framework for low-power approximate logic synthesis.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
HIPE-MAGIC: a technology-aware synthesis and mapping flow for highly parallel execution of memristor-aided LoGIC.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Runtime Deep Model Multiplexing for Reduced Latency and Energy Consumption Inference.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Retiming for High-performance Superconductive Circuits with Register Energy Minimization.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
A Stochastic Framework for Virtualization Layer Deployment in Vehicular Cloud Networks.
Proceedings of the 2020 IEEE International Conference on Communications Workshops, 2020
A Deep Reinforcement Learning Framework for Architectural Exploration: A Routerless NoC Case Study.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
A Timing Uncertainty-Aware Clock Tree Topology Generation Algorithm for Single Flux Quantum Circuits.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
TDP-ADMM: A Timing Driven Placement Approach for Superconductive Electronic Circuits Using Alternating Direction Method of Multipliers.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Hybrid Cell Assignment and Sizing for Power, Area, Delay-Product Optimization of SRAM Arrays.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
QoS guaranteed online management of battery swapping station under dynamic energy pricing.
IET Cyper-Phys. Syst.: Theory & Appl., 2019
Low-power data encoding/decoding for energy-efficient static random access memory design.
IET Circuits Devices Syst., 2019
Optimizing Routerless Network-on-Chip Designs: An Innovative Learning-Based Framework.
CoRR, 2019
CoRR, 2019
Design Space Exploration of Memory Controller Placement in Throughput Processors with Deep Learning.
IEEE Comput. Archit. Lett., 2019
A Hyper-Parameter Based Margin Calculation Algorithm for Single Flux Quantum Logic Cells.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
kNN-CAM: A k-Nearest Neighbors-based Configurable Approximate Floating Point Multiplier.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
BottleNet: A Deep Learning Architecture for Intelligent Mobile Cloud Computing Services.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization.
Proceedings of the International Conference on Computer-Aided Design, 2019
A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Balanced Factorization and Rewriting Algorithms for Synthesizing Single Flux Quantum Logic Circuits.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit Representations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Energy-efficient, low-latency realization of neural networks through boolean logic minimization.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Modeling processor idle times in MPSoC platforms to enable integrated DPM, DVFS, and task scheduling subject to a hard deadline.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Hierarchical, Portfolio Theory-Based Virtual Machine Consolidation in a Compute Cloud.
IEEE Trans. Serv. Comput., 2018
An Efficient False Path-Aware Heuristic Critical Path Selection Method with High Coverage of the Process Variation Space.
ACM Trans. Design Autom. Electr. Syst., 2018
An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes.
IEEE Trans. Emerg. Top. Comput., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Micro, 2018
An Ultra Low-Power Memristive Neuromorphic Circuit for Internet of Things Smart Sensors.
IEEE Internet Things J., 2018
Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications.
Integr., 2018
Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in SRAMs.
IET Circuits Devices Syst., 2018
Energy and Reliability Improvement of Voltage-Based, Clustered, Coarse-Grain Reconfigurable Architectures by Employing Quality-Aware Mapping.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits.
CoRR, 2018
A Graph Partitioning Algorithm with Application in Synthesizing Single Flux Quantum Logic Circuits.
CoRR, 2018
SpRRAM: A Predefined Sparsity Based Memristive Neuromorphic Circuit for Low Power Application.
CoRR, 2018
CoRR, 2018
A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Deploying Customized Data Representation and Approximate Computing in Machine Learning Applications.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Toward Enabling Automated Cognition and Decision-Making in Complex Cyber-Physical Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Power Management of Cache-Enabled Cooperative Base Stations Towards Zero Grid Energy.
Proceedings of the 2018 IEEE International Conference on Communications, 2018
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018
Energy and Performance Efficient Computation Offloading for Deep Neural Networks in a Mobile Cloud Computing Environment.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Energy Consumption and Lifetime Improvement of Coarse-Grained Reconfigurable Architectures Targeting Low-Power Error-Tolerant Applications.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Efficient Critical Path Identification Based on Viability Analysis Method Considering Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2017
CALM: Contention-Aware Latency-Minimal Application Mapping for Flattened Butterfly On-Chip Networks.
ACM Trans. Design Autom. Electr. Syst., 2017
ACM Trans. Design Autom. Electr. Syst., 2017
Optimal Control of PEVs with a Charging Aggregator Considering Regulation Service Provisioning.
ACM Trans. Cyber Phys. Syst., 2017
Hybrid TFET-MOSFET circuit: A solution to design soft-error resilient ultra-low power digital circuit.
Integr., 2017
Hierarchical resource allocation and consolidation framework in a multi-core server cluster using a Markov decision process model.
IET Cyper-Phys. Syst.: Theory & Appl., 2017
CTS2M: concurrent task scheduling and storage management for residential energy consumers under dynamic energy pricing.
IET Cyper-Phys. Syst.: Theory & Appl., 2017
Comput. Electr. Eng., 2017
An energy and area efficient yet high-speed square-root carry select adder structure.
Comput. Electr. Eng., 2017
Gate-all-around FET based 6T SRAM design using a device-circuit co-optimization framework.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Hardware Acceleration of Bayesian Neural Networks Using RAM Based Linear Feedback Gaussian Random Number Generators.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Context-driven power management in cache-enabled base stations using a Bayesian neural network.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017
TruncApp: A truncation-based approximate divider for energy efficient DSP applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Design of multiple fanout clock distribution network for rapid single flux quantum technology.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
High-performance FPGA implementation of equivariant adaptive separation via independence algorithm for Independent Component Analysis.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017
2016
A Comparative Study of the Effectiveness of CPU Consolidation Versus Dynamic Voltage and Frequency Scaling in a Virtualized Multicore Server.
IEEE Trans. Very Large Scale Integr. Syst., 2016
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions.
ACM Trans. Design Autom. Electr. Syst., 2016
Hierarchical SLA-Driven Resource Management for Peak Power-Aware and Energy-Efficient Operation of a Cloud Datacenter.
IEEE Trans. Cloud Comput., 2016
Toward a Profitable Grid-Connected Hybrid Electrical Energy Storage System for Residential Use.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Joint Charge and Thermal Management for Batteries in Portable Systems With Hybrid Power Sources.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Concurrent Task Scheduling and Dynamic Voltage and Frequency Scaling in a Real-Time Embedded System With Energy Harvesting.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Providing Balanced Mapping for Multiple Applications in Many-Core Chip Multiprocessors.
IEEE Trans. Computers, 2016
Model-Free Reinforcement Learning and Bayesian Classification in System-Level Power Management.
IEEE Trans. Computers, 2016
Quantum Inf. Comput., 2016
An efficient temperature dependent hot carrier injection reliability simulation flow.
Microelectron. Reliab., 2016
Simulation of NoC power-gating: Requirements, optimizations, and the Agate simulator.
J. Parallel Distributed Comput., 2016
Integr., 2016
Achieving Energy Efficiency in Datacenters by Virtual Machine Sizing, Replication, and Placement.
Adv. Comput., 2016
Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variation.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Maximizing the performance of NoC-based MPSoCs under total power and power density constraints.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Negotiation-based resource provisioning and task scheduling algorithm for cloud systems.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
A Reinforcement Learning-Based Power Management Framework for Green Computing Data Centers.
Proceedings of the 2016 IEEE International Conference on Cloud Engineering, 2016
Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Optimal co-scheduling of HVAC control and battery management for energy-efficient buildings considering state-of-health degradation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
A Profit Optimization Framework of Energy Storage Devices in Data Centers: Hierarchical Structure and Hybrid Types.
Proceedings of the 9th IEEE International Conference on Cloud Computing, 2016
Efficient Peak Shaving in a Data Center by Joint Optimization of Task Assignment and Energy Storage Management.
Proceedings of the 9th IEEE International Conference on Cloud Computing, 2016
2015
Task Scheduling with Dynamic Voltage and Frequency Scaling for Energy Minimization in the Mobile Cloud Computing Environment.
IEEE Trans. Serv. Comput., 2015
OPLE: A Heuristic Custom Instruction Selection Algorithm Based on Partitioning and Local Exploration of Application Dataflow Graphs.
ACM Trans. Embed. Comput. Syst., 2015
Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits.
Microelectron. Reliab., 2015
Hierarchical power management of a system with autonomously power-managed components using reinforcement learning.
Integr., 2015
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies.
Integr., 2015
A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages.
Int. J. Circuit Theory Appl., 2015
An efficient network on-chip architecture based on isolating local and non-local communications.
Comput. Electr. Eng., 2015
Optimizing fuel economy of hybrid electric vehicles using a Markov decision process model.
Proceedings of the 2015 IEEE Intelligent Vehicles Symposium, 2015
High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistors.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Optimal choice of FinFET devices for energy minimization in deeply-scaled technologies.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Reconfigurable three dimensional photovoltaic panel architecture for solar-powered time extension.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Design and optimization of a reconfigurable power delivery network for large-area, DVS-enabled OLED displays.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Machine Learning-Based Energy Management in a Hybrid Electric Vehicle to Minimize Total Operating Cost.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Analyzing the Dark Silicon Phenomenon in a Many-Core Chip Multi-Processor under Deeply-Scaled Process Technologies.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnect.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Event-driven and sensorless photovoltaic system reconfiguration for electric vehicles.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Joint automatic control of the powertrain and auxiliary systems to enhance the electromobility in hybrid electric vehicles.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Optimal control of PEVs for energy cost minimization and frequency regulation in the smart grid accounting for battery state-of-health degradation.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Reinforcement learning-based control of residential energy storage systems for electric bill minimization.
Proceedings of the 12th Annual IEEE Consumer Communications and Networking Conference, 2015
A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Negotiation-based task scheduling and storage control algorithm to minimize user's electric bills under dynamic prices.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015
A Joint Optimization Framework for Request Scheduling and Energy Storage Management in a Data Center.
Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015
2014
Single-Source, Single-Destination Charge Migration in Hybrid Electrical Energy Storage Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Single-Bit Pseudoparallel Processing Low-Oversampling Delta-Sigma Modulator Suitable for SDR Wireless Transmitters.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Smart Grid, 2014
Architecture and Control Algorithms for Combating Partial Shading in Photovoltaic Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits.
Quantum Inf. Process., 2014
Implementation-aware selection of the custom instruction set for extensible processors.
Microprocess. Microsystems, 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
Impact of Process Variations on Speedup and Maximum Achievable Frequency of Extensible Processors.
ACM J. Emerg. Technol. Comput. Syst., 2014
Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes.
Integr., 2014
Negotiation-based task scheduling to minimize user's electricity bills under dynamic energy prices.
Proceedings of the IEEE Online Conference on Green Communications, 2014
5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near-and Super-Threshold Voltage Regimes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
An efficient semi-analytical current source model for FinFET devices in near/sub-threshold regime considering multiple input switching and stack effect.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the International Symposium on Physical Design, 2014
Smart butterfly: reducing static power dissipation of network-on-chip with core-state-awareness.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Therminator: a thermal simulator for smartphones producing accurate chip and skin temperature maps.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Dynamic thermal management for FinFET-based circuits exploiting the temperature effect inversion phenomenon.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Coordination of the smart grid and distributed data centers: A nested game-based optimization framework.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2014
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2014
Balancing On-Chip Network Latency in Multi-application Mapping for Chip-Multiprocessors.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014
Model-free learning-based online management of hybrid electrical energy storage systems in electric vehicles.
Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014
Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014
Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Power supply and consumption co-optimization of portable embedded systems with hybrid power supply.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Optimal offloading control for a mobile device based on a realistic battery model and semi-markov decision process.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
An optimization framework for data centers to minimize electric bill under day-ahead dynamic energy prices while providing regulation services.
Proceedings of the International Green Computing Conference, 2014
7nm FinFET standard cell layout characterization and power density prediction in near- and super-threshold voltage regimes.
Proceedings of the International Green Computing Conference, 2014
Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Minimizing state-of-health degradation in hybrid electrical energy storage systems with arbitrary source and load profiles.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
FEPMA: Fine-grained event-driven power meter for android smartphones based on device driver layer event monitoring.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Improving efficiency of extensible processors by using approximate custom instructions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Concurrent placement, capacity provisioning, and request flow control for a distributed cloud infrastructure.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Cost-effective design of a hybrid electrical energy storage system for electric vehicles.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
Trace-Based Analysis and Prediction of Cloud Computing User Behavior Using the Fractal Modeling Technique.
Proceedings of the 2014 IEEE International Congress on Big Data, Anchorage, AK, USA, June 27, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Semi-analytical current source modeling of FinFET devices operating in near/sub-threshold regime with independent gate control and considering process variation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Energy and Performance-Aware Task Scheduling in a Mobile Cloud Computing Environment.
Proceedings of the 2014 IEEE 7th International Conference on Cloud Computing, Anchorage, AK, USA, June 27, 2014
2013
Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Accurate Modeling of the Delay and Energy Overhead of Dynamic Voltage and Frequency Scaling in Modern Microprocessors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip-Flops Under the Negative Bias Temperature Instability Effect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Computers, 2013
Microprocess. Microsystems, 2013
Found. Trends Electron. Des. Autom., 2013
A new merit function for custom instruction selection under an area budget constraint.
Des. Autom. Embed. Syst., 2013
A Nested Two Stage Game-Based Optimization Framework in Mobile Cloud Computing System.
Proceedings of the Seventh IEEE International Symposium on Service-Oriented System Engineering, 2013
Proceedings of the Reversible Computation - 5th International Conference, 2013
A nested game-based optimization framework for electricity retailers in the smart grid with residential users and PEVs.
Proceedings of the IEEE Online Conference on Green Communications, OnlineGreenComm 2013, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Resource allocation and consolidation in a multi-core server cluster using a Markov decision process model.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
A framework of concurrent task scheduling and dynamic voltage and frequency scaling in real-time embedded systems with energy harvesting.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Platform-dependent, leakage-aware control of the driving current of embedded thermoelectric coolers.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
A sequential game perspective and optimization of the smart grid with distributed data centers.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2013
A game-theoretic price determination algorithm for utility companies serving a community in smart grid.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2013
Semi-analytical current source modeling of near-threshold operating logic cells considering process variations.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Dynamic thermal management in mobile devices considering the thermal coupling between battery and application processor.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
A semi-Markovian decision process based control method for offloading tasks from mobile devices to the cloud.
Proceedings of the 2013 IEEE Global Communications Conference, 2013
Reinforcement Learning-Based Dynamic Power Management of a Battery-Powered System Supplying Multiple Active Modes.
Proceedings of the Seventh UKSim/AMSS European Modelling Symposium, 2013
Capturing and mitigating the NBTI effect during the design flow for extensible processors.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
Adaptive thermal management for portable system batteries by forced convection cooling.
Proceedings of the Design, Automation and Test in Europe, 2013
Optimal control of a grid-connected hybrid electrical energy storage system for homes.
Proceedings of the Design, Automation and Test in Europe, 2013
Capital cost-aware design and partial shading-aware architecture optimization of a reconfigurable photovoltaic system.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Designing a residential hybrid electrical energy storage system based on the energy buffering strategy.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
An energy and deadline aware resource provisioning, scheduling and optimization framework for cloud systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
Force-directed geographical load balancing and scheduling for batch jobs in distributed datacenters.
Proceedings of the 2013 IEEE International Conference on Cluster Computing, 2013
An optimal control policy in a mobile cloud computing system based on stochastic data.
Proceedings of the IEEE 2nd International Conference on Cloud Networking, 2013
Maximizing return on investment of a grid-connected hybrid electrical energy storage system.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
An efficient scheduling algorithm for multiple charge migration tasks in hybrid electrical energy storage systems.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Online estimation of the remaining energy capacity in mobile systems considering system-wide power consumption and battery characteristics.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 2013 IEEE Sixth International Conference on Cloud Computing, Santa Clara, CA, USA, June 28, 2013
Geographical Load Balancing for Online Service Applications in Distributed Datacenters.
Proceedings of the 2013 IEEE Sixth International Conference on Cloud Computing, Santa Clara, CA, USA, June 28, 2013
2012
Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Probability calculation of read failures in nano-scaled SRAM cells under process variations.
Microelectron. Reliab., 2012
An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling.
J. Zhejiang Univ. Sci. C, 2012
Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution.
IET Circuits Devices Syst., 2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
Profit maximization for utility companies in an oligopolistic energy market with dynamic prices.
Proceedings of the IEEE Online Conference on Green Communications, 2012
Enhancing efficiency and robustness of a photovoltaic power system under partial shading.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Dynamic reconfiguration of photovoltaic energy harvesting system in hybrid electric vehicles.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
A study of the effectiveness of CPU consolidation in a virtualized multi-core server system.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Concurrent optimization of consumer's electrical energy bill and producer's power generation cost under a dynamic pricing model.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuits.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Robust optimization of a Chip Multiprocessor's performance under power and thermal constraints.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Battery cell configuration for organic light emitting diode display in modern smartphones and tablet-PCs.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Multiple-source and multiple-destination charge migration in hybrid electrical energy storage systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
An architecture-level approach for mitigating the impact of process variations on extensible processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Near-optimal, dynamic module reconfiguration in a photovoltaic system to combat partial shading effects.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 12th IEEE/ACM International Symposium on Cluster, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 2012 IEEE Fifth International Conference on Cloud Computing, 2012
Energy-Efficient Virtual Machine Replication and Placement in a Cloud Computing System.
Proceedings of the 2012 IEEE Fifth International Conference on Cloud Computing, 2012
2011
Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
ACM Trans. Design Autom. Electr. Syst., 2011
Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the IEEE Second International Conference on Smart Grid Communications, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 2011 International Symposium on Physical Design, 2011
Charge migration efficiency optimization in hybrid electrical energy storage (HEES) systems.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 31st IEEE International Conference on Distributed Computing Systems Workshops (ICDCS 2011 Workshops), 2011
Balanced reconfiguration of storage banks in a hybrid electrical energy storage system.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Deriving a near-optimal power management policy using model-free reinforcement learning and Bayesian classification.
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 48th Design Automation Conference, 2011
Multi-dimensional SLA-Based Resource Allocation for Multi-tier Cloud Computing Systems.
Proceedings of the IEEE International Conference on Cloud Computing, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
A Markovian Decision-Based Approach for Extending the Lifetime of a Network of Battery-Powered Mobile Devices by Remote Processing.
J. Low Power Electron., 2010
IEICE Electron. Express, 2010
Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Minimizing energy consumption of a chip multiprocessor through simultaneous core consolidation and DVFS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Analysis and optimization of sequential circuit element to combat single-event timing upsets.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 39th International Conference on Parallel Processing, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition times.
Proceedings of the Design, Automation and Test in Europe, 2010
Efficient representation, stratification, and compression of variational CSM library waveforms using Robust Principle Component Analysis.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Optimal Design of the Power-Delivery Network for Multiple Voltage-Island System-on-Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips.
J. Low Power Electron., 2009
A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution.
J. Low Power Electron., 2009
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors.
Proceedings of the 27th International Conference on Computer Design, 2009
Green computing: reducing energy cost and carbon footprint of information processing systems.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 6th IEEE Consumer Communications and Networking Conference, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
ACM Trans. Design Autom. Electr. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
J. Low Power Electron., 2008
Heterogeneous modulation for trading-off energy balancing with bandwidth efficiency in hierarchical sensor networks.
Proceedings of the 9th IEEE International Symposium on a World of Wireless, 2008
High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008
Improving the Efficiency of Power Management Techniques by Using Bayesian Classification.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Probabilistic error propagation in logic circuits using the Boolean difference calculus.
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Statistical timing analysis of flip-flops considering codependent setup and hold times.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Introduction to special issue on demonstrable software systems and hardware platforms.
ACM Trans. Design Autom. Electr. Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
A Unified Framework for System-Level Design: Modeling and Performance Optimization of Scalable Networking Systems.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Design of an efficient power delivery network in an soc to enable dynamic power management.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Active bank switching for temperature control of the register file in a microprocessor.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries.
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
ACM Trans. Design Autom. Electr. Syst., 2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Cycle-Based Decomposition of Markov Chains With Applications to Low-Power Synthesis and Sequence Compaction for Finite State Machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proc. IEEE, 2006
Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Dynamic voltage and frequency management based on variable update intervals for frequency setting.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Determining the optimal timeout values for a power-managed system based on the theory of Markovian processes: offline and online algorithms.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
B<sup>2</sup>Sim: : a fast micro-architecture simulator based on basic block characterization.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
A Leakage-aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect.
J. Low Power Electron., 2005
J. Low Power Electron., 2005
IEICE Trans. Electron., 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
QoM and lifetime-constrained random deployment of sensor networks for minimum energy consumption.
Proceedings of the Fourth International Symposium on Information Processing in Sensor Networks, 2005
Proceedings of the Fourth International Symposium on Information Processing in Sensor Networks, 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Consumer Electron., 2004
Power minimization in a backlit TFT-LCD display by concurrent brightness and contrast scaling.
IEEE Trans. Consumer Electron., 2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Des. Test Comput., 2004
Proceedings of the 2004 IEEE Wireless Communications and Networking Conference , 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times.
Proceedings of the 2004 Design, 2004
Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling.
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the Ultra Low-Power Electronics and Design, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Proceedings of the 2003 IEEE Wireless Communications and Networking, 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Energy-Aware Wireless Video Streaming.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003
Extending the lifetime of a network of battery-powered mobile devices by remote processing: a markovian decision-based approach.
Proceedings of the 40th Design Automation Conference, 2003
Technology mapping for low leakage power and high speed with hot-carrier effect consideration.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
J. Circuits Syst. Comput., 2002
J. Circuits Syst. Comput., 2002
Sci. China Ser. F Inf. Sci., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits<sup>1, 2</sup>.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 2002 Design, 2002
EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses.
Proceedings of the 2002 Design, 2002
A comprehensive study of energy dissipation in lossy transmission lines driven by CMOS inverters.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
Estimation of peak power dissipation in VLSI circuits using thelimiting distributions of extreme order statistics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 2001 International Symposium on Physical Design, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service.
Proceedings of the 38th Design Automation Conference, 2001
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs.
Proceedings of the 38th Design Automation Conference, 2001
Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Proceedings of ASP-DAC 2001, 2001
Proceedings of ASP-DAC 2001, 2001
Proceedings of ASP-DAC 2001, 2001
Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points.
Proceedings of ASP-DAC 2001, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Stochastic sequential machine synthesis with application to constrained sequence generation.
ACM Trans. Design Autom. Electr. Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Electronic design automation at the turn of the century: accomplishments and vision of the future.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Proceedings of ASP-DAC 2000, 2000
Proceedings of ASP-DAC 2000, 2000
Analysis of power-clocked CMOS with application to the design of energy-recovery circuits.
Proceedings of ASP-DAC 2000, 2000
1999
Proceedings of the VLSI Handbook., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 1999 International Symposium on Physical Design, 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 1999 Design, 1999
MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search.
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Integr., 1998
Calculation of ramp response of lossy transmission lines using two-port network functions.
Proceedings of the 1998 International Symposium on Physical Design, 1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the 1998 Design, 1998
Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation.
Proceedings of the 1998 Design, 1998
A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together.
Proceedings of the 35th Conference on Design Automation, 1998
Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics.
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the 35th Conference on Design Automation, 1998
A New Design for Double Edge Triggered Flip-flops.
Proceedings of the ASP-DAC '98, 1998
Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions (Embedded Tutorial).
Proceedings of the ASP-DAC '98, 1998
Proceedings of the ASP-DAC '98, 1998
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits.
Proceedings of the ASP-DAC '98, 1998
1997
IEEE Trans. Very Large Scale Integr. Syst., 1997
Integr., 1997
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Composite sequence compaction for finite-state machines using block entropy and high-order Markov models.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Statistical Estimation of the Cumulative Distribution Function for Power Dissipation in VLSI Cirucits.
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].
IEEE Trans. Very Large Scale Integr. Syst., 1996
ACM Trans. Design Autom. Electr. Syst., 1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
IEEE Trans. Computers, 1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
Proceedings of the conference on European design automation, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
Proceedings of the 33st Conference on Design Automation, 1996
Proceedings of the 33st Conference on Design Automation, 1996
Proceedings of the 33st Conference on Design Automation, 1996
Proceedings of the 33st Conference on Design Automation, 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 32st Conference on Design Automation, 1995
1994
Power efficient technology decomposition and mapping under an extended power consumption model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs.
Proceedings of the 31st Conference on Design Automation, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the European Design Automation Conference 1993, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
Proceedings of the conference on European design automation, 1992
A Near Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints.
Proceedings of the 29th Design Automation Conference, 1992
1991
A Flow-Oriented Approach to the Placement of Boolean Networks.
Proceedings of the VLSI 91, 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991
Proceedings of the 28th Design Automation Conference, 1991
1990
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989
1988
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988