Massoud Pedram

According to our database1, Massoud Pedram authored at least 637 papers between 1988 and 2020.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2001, "For contributions to the theory and practice of low-power design and CAD.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2020
DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy.
IEEE Trans. VLSI Syst., 2020

RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory.
IEEE Trans. VLSI Syst., 2020

Res-DNN: A Residue Number System-Based DNN Accelerator Unit.
IEEE Trans. on Circuits and Systems, 2020

Block-Based Carry Speculative Approximate Adder for Energy-Efficient Applications.
IEEE Trans. on Circuits and Systems, 2020

Energy Efficiency in 5G Cellular Network Systems.
IEEE Design & Test, 2020

NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework.
CoRR, 2020

Efficient Training of Deep Convolutional Neural Networks by Augmentation in Embedding Space.
CoRR, 2020

qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit.
CoRR, 2020

Pre-defined Sparsity for Low-Complexity Convolutional Neural Networks.
CoRR, 2020

Run-time Deep Model Multiplexing.
CoRR, 2020

2019
TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier.
IEEE Trans. VLSI Syst., 2019

A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders.
IEEE Trans. on Circuits and Systems, 2019

Hybrid Cell Assignment and Sizing for Power, Area, Delay-Product Optimization of SRAM Arrays.
IEEE Trans. on Circuits and Systems, 2019

OCTAN: An On-Chip Training Algorithm for Memristive Neuromorphic Circuits.
IEEE Trans. on Circuits and Systems, 2019

ACHILLES: Accuracy-Aware High-Level Synthesis Considering Online Quality Management.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

QoS guaranteed online management of battery swapping station under dynamic energy pricing.
IET Cyper-Phys. Syst.: Theory & Appl., 2019

Low-power data encoding/decoding for energy-efficient static random access memory design.
IET Circuits, Devices & Systems, 2019

Energy-aware Scheduling of Jobs in Heterogeneous Cluster Systems Using Deep Reinforcement Learning.
CoRR, 2019

Coarse2Fine: A Two-stage Training Method for Fine-grained Visual Classification.
CoRR, 2019

Optimizing Routerless Network-on-Chip Designs: An Innovative Learning-Based Framework.
CoRR, 2019

Energy-Aware Scheduling of Task Graphs with Imprecise Computations and End-to-End Deadlines.
CoRR, 2019

Space Expansion of Feature Selection for Designing more Accurate Error Predictors.
CoRR, 2019

Design Space Exploration of Memory Controller Placement in Throughput Processors with Deep Learning.
Computer Architecture Letters, 2019

A Hyper-Parameter Based Margin Calculation Algorithm for Single Flux Quantum Logic Cells.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

kNN-CAM: A k-Nearest Neighbors-based Configurable Approximate Floating Point Multiplier.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Towards Collaborative Intelligence Friendly Architectures for Deep Learning.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

BottleNet: A Deep Learning Architecture for Intelligent Mobile Cloud Computing Services.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification Framework.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization.
Proceedings of the International Conference on Computer-Aided Design, 2019

A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Balanced Factorization and Rewriting Algorithms for Synthesizing Single Flux Quantum Logic Circuits.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit Representations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Energy-efficient, low-latency realization of neural networks through boolean logic minimization.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Modeling processor idle times in MPSoC platforms to enable integrated DPM, DVFS, and task scheduling subject to a hard deadline.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

A Meta-Learning Approach for Custom Model Training.
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019

2018
Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications.
IEEE Trans. VLSI Syst., 2018

Hierarchical, Portfolio Theory-Based Virtual Machine Consolidation in a Compute Cloud.
IEEE Trans. Services Computing, 2018

An Efficient False Path-Aware Heuristic Critical Path Selection Method with High Coverage of the Process Variation Space.
ACM Trans. Design Autom. Electr. Syst., 2018

An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes.
IEEE Trans. Emerging Topics Comput., 2018

RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder.
IEEE Trans. on Circuits and Systems, 2018

TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures.
IEEE Micro, 2018

An Ultra Low-Power Memristive Neuromorphic Circuit for Internet of Things Smart Sensors.
IEEE Internet of Things Journal, 2018

Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications.
Integr., 2018

Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in SRAMs.
IET Circuits, Devices & Systems, 2018

Energy and Reliability Improvement of Voltage-Based, Clustered, Coarse-Grain Reconfigurable Architectures by Employing Quality-Aware Mapping.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits.
CoRR, 2018

Gradient Agreement as an Optimization Objective for Meta-Learning.
CoRR, 2018

A Graph Partitioning Algorithm with Application in Synthesizing Single Flux Quantum Logic Circuits.
CoRR, 2018

SpRRAM: A Predefined Sparsity Based Memristive Neuromorphic Circuit for Low Power Application.
CoRR, 2018

NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inference.
CoRR, 2018

JointDNN: An Efficient Training and Inference Engine for Intelligent Mobile Cloud Computing Services.
CoRR, 2018

A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

An Energy-Efficient, Yet Highly-Accurate, Approximate Non-Iterative Divider.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Deploying Customized Data Representation and Approximate Computing in Machine Learning Applications.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

SFQmap: A Technology Mapping Tool for Single Flux Quantum Logic Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Toward Enabling Automated Cognition and Decision-Making in Complex Cyber-Physical Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Opportunities for Machine Learning in Electronic Design Automation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design automation methodology and tools for superconductive electronics.
Proceedings of the International Conference on Computer-Aided Design, 2018

Power Management of Cache-Enabled Cooperative Base Stations Towards Zero Grid Energy.
Proceedings of the 2018 IEEE International Conference on Communications, 2018

Energy-Efficient Computing: Datacenters, Mobile Devices, and Mobile Clouds.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Energy and Performance Efficient Computation Offloading for Deep Neural Networks in a Mobile Cloud Computing Environment.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Energy Consumption and Lifetime Improvement of Coarse-Grained Reconfigurable Architectures Targeting Low-Power Error-Tolerant Applications.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Accurate margin calculation for single flux quantum logic cells.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

FFT-based deep learning deployment in embedded systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

VIBNN: Hardware Acceleration of Bayesian Neural Networks.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing.
IEEE Trans. VLSI Syst., 2017

Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers.
IEEE Trans. VLSI Syst., 2017

Efficient Critical Path Identification Based on Viability Analysis Method Considering Process Variations.
IEEE Trans. VLSI Syst., 2017

CALM: Contention-Aware Latency-Minimal Application Mapping for Flattened Butterfly On-Chip Networks.
ACM Trans. Design Autom. Electr. Syst., 2017

TEI-power: Temperature Effect Inversion-Aware Dynamic Thermal Management.
ACM Trans. Design Autom. Electr. Syst., 2017

Optimal Control of PEVs with a Charging Aggregator Considering Regulation Service Provisioning.
TCPS, 2017

Hybrid TFET-MOSFET circuit: A solution to design soft-error resilient ultra-low power digital circuit.
Integr., 2017

An optimal energy co-scheduling framework for smart buildings.
Integr., 2017

Hierarchical resource allocation and consolidation framework in a multi-core server cluster using a Markov decision process model.
IET Cyper-Phys. Syst.: Theory & Appl., 2017

CTS2M: concurrent task scheduling and storage management for residential energy consumers under dynamic energy pricing.
IET Cyper-Phys. Syst.: Theory & Appl., 2017

LETAM: A low energy truncation-based approximate multiplier.
Comput. Electr. Eng., 2017

An energy and area efficient yet high-speed square-root carry select adder structure.
Comput. Electr. Eng., 2017

Hardware Acceleration of Bayesian Neural Networks Using RAM Based Linear Feedback Gaussian Random Number Generators.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Pilot Register File: Energy Efficient Partitioned Register File for GPUs.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Context-driven power management in cache-enabled base stations using a Bayesian neural network.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

TruncApp: A truncation-based approximate divider for energy efficient DSP applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A thermally-aware energy minimization methodology for global interconnects.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Robust neuromorphic computing in the presence of process variation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Design of multiple fanout clock distribution network for rapid single flux quantum technology.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

High-performance FPGA implementation of equivariant adaptive separation via independence algorithm for Independent Component Analysis.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
A Comparative Study of the Effectiveness of CPU Consolidation Versus Dynamic Voltage and Frequency Scaling in a Virtualized Multicore Server.
IEEE Trans. VLSI Syst., 2016

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels.
IEEE Trans. VLSI Syst., 2016

Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions.
ACM Trans. Design Autom. Electr. Syst., 2016

Hierarchical SLA-Driven Resource Management for Peak Power-Aware and Energy-Efficient Operation of a Cloud Datacenter.
IEEE Trans. Cloud Computing, 2016

Toward a Profitable Grid-Connected Hybrid Electrical Energy Storage System for Residential Use.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Joint Charge and Thermal Management for Batteries in Portable Systems With Hybrid Power Sources.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Concurrent Task Scheduling and Dynamic Voltage and Frequency Scaling in a Real-Time Embedded System With Energy Harvesting.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Providing Balanced Mapping for Multiple Applications in Many-Core Chip Multiprocessors.
IEEE Trans. Computers, 2016

Model-Free Reinforcement Learning and Bayesian Classification in System-Level Power Management.
IEEE Trans. Computers, 2016

Squash 2: a hierarchical scalable quantum mapper considering ancilla sharing.
Quantum Information & Computation, 2016

An efficient temperature dependent hot carrier injection reliability simulation flow.
Microelectron. Reliab., 2016

Simulation of NoC power-gating: Requirements, optimizations, and the Agate simulator.
J. Parallel Distributed Comput., 2016

A comparative study on performance and reliability of 32-bit binary adders.
Integr., 2016

Achieving Energy Efficiency in Datacenters by Virtual Machine Sizing, Replication, and Placement.
Advances in Computers, 2016

Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variation.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Maximizing the performance of NoC-based MPSoCs under total power and power density constraints.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Negotiation-based resource provisioning and task scheduling algorithm for cloud systems.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

An efficient timing analysis model for 6T FinFET SRAM using current-based method.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Power-aware virtual machine mapping in the data-center-on-a-chip paradigm.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

A Reinforcement Learning-Based Power Management Framework for Green Computing Data Centers.
Proceedings of the 2016 IEEE International Conference on Cloud Engineering, 2016

Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

SEERAD: A high speed yet energy-efficient rounding-based approximate divider.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Optimal co-scheduling of HVAC control and battery management for energy-efficient buildings considering state-of-health degradation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

A Profit Optimization Framework of Energy Storage Devices in Data Centers: Hierarchical Structure and Hybrid Types.
Proceedings of the 9th IEEE International Conference on Cloud Computing, 2016

Efficient Peak Shaving in a Data Center by Joint Optimization of Task Assignment and Energy Storage Management.
Proceedings of the 9th IEEE International Conference on Cloud Computing, 2016

2015
Task Scheduling with Dynamic Voltage and Frequency Scaling for Energy Minimization in the Mobile Cloud Computing Environment.
IEEE Trans. Services Computing, 2015

OPLE: A Heuristic Custom Instruction Selection Algorithm Based on Partitioning and Local Exploration of Application Dataflow Graphs.
ACM Trans. Embedded Comput. Syst., 2015

Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries.
IEEE Trans. on Circuits and Systems, 2015

Optimizing a Reconfigurable Power Distribution Network in a Multicore Platform.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

CSAM: A clock skew-aware aging mitigation technique.
Microelectron. Reliab., 2015

Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits.
Microelectron. Reliab., 2015

Hierarchical power management of a system with autonomously power-managed components using reinforcement learning.
Integr., 2015

Design of NBTI-resilient extensible processors.
Integr., 2015

A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies.
Integr., 2015

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages.
I. J. Circuit Theory and Applications, 2015

An efficient network on-chip architecture based on isolating local and non-local communications.
Comput. Electr. Eng., 2015

Optimizing fuel economy of hybrid electric vehicles using a Markov decision process model.
Proceedings of the 2015 IEEE Intelligent Vehicles Symposium, 2015

High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistors.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Design optimization of sense amplifiers using deeply-scaled FinFET devices.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Optimal choice of FinFET devices for energy minimization in deeply-scaled technologies.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Reconfigurable three dimensional photovoltaic panel architecture for solar-powered time extension.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Design and optimization of a reconfigurable power delivery network for large-area, DVS-enabled OLED displays.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

ThermTap: An online power analyzer and thermal simulator for Android devices.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Machine Learning-Based Energy Management in a Hybrid Electric Vehicle to Minimize Total Operating Cost.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Power punch: Towards non-blocking power-gating of NoC routers.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Analyzing the Dark Silicon Phenomenon in a Many-Core Chip Multi-Processor under Deeply-Scaled Process Technologies.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

TAPP: temperature-aware application mapping for NoC-based many-core processors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnect.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Event-driven and sensorless photovoltaic system reconfiguration for electric vehicles.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A thermal stress-aware algorithm for power and temperature management of MPSoCs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Accurate electrothermal modeling of thermoelectric generators.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Power-efficient control of thermoelectric coolers considering distributed hot spots.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Joint automatic control of the powertrain and auxiliary systems to enhance the electromobility in hybrid electric vehicles.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Optimal control of PEVs for energy cost minimization and frequency regulation in the smart grid accounting for battery state-of-health degradation.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Reinforcement learning-based control of residential energy storage systems for electric bill minimization.
Proceedings of the 12th Annual IEEE Consumer Communications and Networking Conference, 2015

A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Negotiation-based task scheduling and storage control algorithm to minimize user's electric bills under dynamic prices.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Hierarchical Deployment and Control of Energy Storage Devices in Data Centers.
Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015

A Joint Optimization Framework for Request Scheduling and Energy Storage Management in a Data Center.
Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015

2014
Single-Source, Single-Destination Charge Migration in Hybrid Electrical Energy Storage Systems.
IEEE Trans. VLSI Syst., 2014

Single-Bit Pseudoparallel Processing Low-Oversampling Delta-Sigma Modulator Suitable for SDR Wireless Transmitters.
IEEE Trans. VLSI Syst., 2014

Adaptive Control for Energy Storage Systems in Households With Photovoltaic Modules.
IEEE Trans. Smart Grid, 2014

Architecture and Control Algorithms for Combating Partial Shading in Photovoltaic Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Optimizing the Power Delivery Network in a Smartphone Platform.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits.
Quantum Information Processing, 2014

Implementation-aware selection of the custom instruction set for extensible processors.
Microprocess. Microsystems, 2014

Cofactor Sharing for Reversible Logic Synthesis.
JETC, 2014

Impact of Process Variations on Speedup and Maximum Achievable Frequency of Extensible Processors.
JETC, 2014

Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes.
Integr., 2014

Designing Fault-Tolerant Photovoltaic Systems.
IEEE Design & Test, 2014

Negotiation-based task scheduling to minimize user's electricity bills under dynamic energy prices.
Proceedings of the IEEE Online Conference on Green Communications, 2014

5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near-and Super-Threshold Voltage Regimes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

An efficient semi-analytical current source model for FinFET devices in near/sub-threshold regime considering multiple input switching and stack effect.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Interconnect length estimation in VLSI designs: a retrospective.
Proceedings of the International Symposium on Physical Design, 2014

Smart butterfly: reducing static power dissipation of network-on-chip with core-state-awareness.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Therminator: a thermal simulator for smartphones producing accurate chip and skin temperature maps.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Dynamic thermal management for FinFET-based circuits exploiting the temperature effect inversion phenomenon.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Fast photovoltaic array reconfiguration for partial solar powered vehicles.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Coordination of the smart grid and distributed data centers: A nested game-based optimization framework.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2014

An electricity trade model for microgrid communities in smart grid.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2014

Balancing On-Chip Network Latency in Multi-application Mapping for Chip-Multiprocessors.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

Model-free learning-based online management of hybrid electrical energy storage systems in electric vehicles.
Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014

Resource allocation optimization in a data center with energy storage devices.
Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014

Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Low write-energy STT-MRAMs using FinFET-based access transistors.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Power supply and consumption co-optimization of portable embedded systems with hybrid power supply.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Reinforcement learning based power management for hybrid electric vehicles.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Optimal offloading control for a mobile device based on a realistic battery model and semi-markov decision process.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

An optimization framework for data centers to minimize electric bill under day-ahead dynamic energy prices while providing regulation services.
Proceedings of the International Green Computing Conference, 2014

7nm FinFET standard cell layout characterization and power density prediction in near- and super-threshold voltage regimes.
Proceedings of the International Green Computing Conference, 2014

Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Squash: a scalable quantum mapper considering ancilla sharing.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Optimal design and management of a smart residential PV and energy storage system.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Application mapping for express channel-based networks-on-chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Minimizing state-of-health degradation in hybrid electrical energy storage systems with arbitrary source and load profiles.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

VRCon: Dynamic reconfiguration of voltage regulators in a multicore platform.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

FEPMA: Fine-grained event-driven power meter for android smartphones based on device driver layer event monitoring.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Improving efficiency of extensible processors by using approximate custom instructions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Concurrent placement, capacity provisioning, and request flow control for a distributed cloud infrastructure.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Power-Aware Deployment and Control of Forced-Convection and Thermoelectric Coolers.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Cost-effective design of a hybrid electrical energy storage system for electric vehicles.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Prediction and control of bursty cloud workloads: A fractal framework.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Trace-Based Analysis and Prediction of Cloud Computing User Behavior Using the Fractal Modeling Technique.
Proceedings of the 2014 IEEE International Congress on Big Data, Anchorage, AK, USA, June 27, 2014

Qubit placement to minimize communication overhead in 2D quantum architectures.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Semi-analytical current source modeling of FinFET devices operating in near/sub-threshold regime with independent gate control and considering process variation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Energy and Performance-Aware Task Scheduling in a Mobile Cloud Computing Environment.
Proceedings of the 2014 IEEE 7th International Conference on Cloud Computing, Anchorage, AK, USA, June 27, 2014

2013
Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits.
IEEE Trans. VLSI Syst., 2013

Charge Allocation in Hybrid Electrical Energy Storage Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Dynamic Driver Supply Voltage Scaling for Organic Light Emitting Diode Displays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Accurate Modeling of the Delay and Energy Overhead of Dynamic Voltage and Frequency Scaling in Modern Microprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip-Flops Under the Negative Bias Temperature Instability Effect.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

NFRA: Generalized Network Flow-Based Resource Allocation for Hosting Centers.
IEEE Trans. Computers, 2013

Reversible logic synthesis by quantum rotation gates.
Quantum Information & Computation, 2013

Considering the effect of process variations during the ISA extension design flow.
Microprocess. Microsystems, 2013

Computer-Aided Design and Optimization of Hybrid Energy Storage Systems.
Foundations and Trends in Electronic Design Automation, 2013

A new merit function for custom instruction selection under an area budget constraint.
Design Autom. for Emb. Sys., 2013

Linear-Depth Quantum Circuits for n-qubit Toffoli gates with no Ancilla
CoRR, 2013

A Nested Two Stage Game-Based Optimization Framework in Mobile Cloud Computing System.
Proceedings of the Seventh IEEE International Symposium on Service-Oriented System Engineering, 2013

Constant-Factor Optimization of Quantum Adders on 2D Quantum Architectures.
Proceedings of the Reversible Computation - 5th International Conference, 2013

A nested game-based optimization framework for electricity retailers in the smart grid with residential users and PEVs.
Proceedings of the IEEE Online Conference on Green Communications, OnlineGreenComm 2013, 2013

Hierarchical dynamic power management using model-free reinforcement learning.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Resource allocation and consolidation in a multi-core server cluster using a Markov decision process model.
Proceedings of the International Symposium on Quality Electronic Design, 2013

SIMES: A simulator for hybrid electrical energy storage systems.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Maximum power transfer tracking in a solar USB charger for smartphones.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

A framework of concurrent task scheduling and dynamic voltage and frequency scaling in real-time embedded systems with energy harvesting.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Platform-dependent, leakage-aware control of the driving current of embedded thermoelectric coolers.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

A sequential game perspective and optimization of the smart grid with distributed data centers.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2013

A game-theoretic price determination algorithm for utility companies serving a community in smart grid.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2013

Semi-analytical current source modeling of near-threshold operating logic cells considering process variations.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Dynamic thermal management in mobile devices considering the thermal coupling between battery and application processor.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A semi-Markovian decision process based control method for offloading tasks from mobile devices to the cloud.
Proceedings of the 2013 IEEE Global Communications Conference, 2013

Reinforcement Learning-Based Dynamic Power Management of a Battery-Powered System Supplying Multiple Active Modes.
Proceedings of the Seventh UKSim/AMSS European Modelling Symposium, 2013

Capturing and mitigating the NBTI effect during the design flow for extensible processors.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

Adaptive thermal management for portable system batteries by forced convection cooling.
Proceedings of the Design, Automation and Test in Europe, 2013

Optimal control of a grid-connected hybrid electrical energy storage system for homes.
Proceedings of the Design, Automation and Test in Europe, 2013

Capital cost-aware design and partial shading-aware architecture optimization of a reconfigurable photovoltaic system.
Proceedings of the Design, Automation and Test in Europe, 2013

Reversible logic synthesis of k-input, m-output lookup tables.
Proceedings of the Design, Automation and Test in Europe, 2013

Creating a sustainable information and communication infrastructure.
Proceedings of the Design, Automation and Test in Europe, 2013

Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

LEQA: latency estimation for a quantum algorithm mapped to a quantum circuit fabric.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Designing a residential hybrid electrical energy storage system based on the energy buffering strategy.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

An energy and deadline aware resource provisioning, scheduling and optimization framework for cloud systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Force-directed geographical load balancing and scheduling for batch jobs in distributed datacenters.
Proceedings of the 2013 IEEE International Conference on Cluster Computing, 2013

An optimal control policy in a mobile cloud computing system based on stochastic data.
Proceedings of the IEEE 2nd International Conference on Cloud Networking, 2013

Maximizing return on investment of a grid-connected hybrid electrical energy storage system.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

An efficient scheduling algorithm for multiple charge migration tasks in hybrid electrical energy storage systems.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Online estimation of the remaining energy capacity in mobile systems considering system-wide power consumption and battery characteristics.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Hierarchical Virtual Machine Consolidation in a Cloud Computing System.
Proceedings of the 2013 IEEE Sixth International Conference on Cloud Computing, Santa Clara, CA, USA, June 28, 2013

Geographical Load Balancing for Online Service Applications in Distributed Datacenters.
Proceedings of the 2013 IEEE Sixth International Conference on Cloud Computing, Santa Clara, CA, USA, June 28, 2013

2012
Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating.
IEEE Trans. VLSI Syst., 2012

Energy-Efficient Datacenters.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Probability calculation of read failures in nano-scaled SRAM cells under process variations.
Microelectron. Reliab., 2012

An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling.
Journal of Zhejiang University - Science C, 2012

Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution.
IET Circuits, Devices & Systems, 2012

Dynamic Power Management of a Computer with Self Power-Managed Components.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Profit maximization for utility companies in an oligopolistic energy market with dynamic prices.
Proceedings of the IEEE Online Conference on Green Communications, 2012

Enhancing efficiency and robustness of a photovoltaic power system under partial shading.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Dynamic reconfiguration of photovoltaic energy harvesting system in hybrid electric vehicles.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Battery management for grid-connected PV systems with a battery.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Power conversion efficiency characterization and optimization for smartphones.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

A study of the effectiveness of CPU consolidation in a virtualized multi-core server system.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Concurrent optimization of consumer's electrical energy bill and producer's power generation cost under a dynamic pricing model.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2012

Reinforcement learning based dynamic power management with a hybrid power supply.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuits.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Robust optimization of a Chip Multiprocessor's performance under power and thermal constraints.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Battery cell configuration for organic light emitting diode display in modern smartphones and tablet-PCs.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Online fault detection and tolerance for photovoltaic energy harvesting systems.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

State of health aware charge management in hybrid electrical energy storage systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Multiple-source and multiple-destination charge migration in hybrid electrical energy storage systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

An architecture-level approach for mitigating the impact of process variations on extensible processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Near-optimal, dynamic module reconfiguration in a photovoltaic system to combat partial shading effects.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Networked architecture for hybrid electrical energy storage systems.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

SLA-based Optimization of Power and Migration Cost in Cloud Computing.
Proceedings of the 12th IEEE/ACM International Symposium on Cluster, 2012

Charge replacement in hybrid electrical energy storage systems.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Portfolio Theory-Based Resource Assignment in a Cloud Computing System.
Proceedings of the 2012 IEEE Fifth International Conference on Cloud Computing, 2012

Energy-Efficient Virtual Machine Replication and Placement in a Cloud Computing System.
Proceedings of the 2012 IEEE Fifth International Conference on Cloud Computing, 2012

2011
Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs.
IEEE Trans. VLSI Syst., 2011

Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling.
IEEE Trans. VLSI Syst., 2011

Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage.
IEEE Trans. VLSI Syst., 2011

Call for papers: Verification issue and challenges with multicore systems.
ACM Trans. Design Autom. Electr. Syst., 2011

Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Demand-side load scheduling incentivized by dynamic energy prices.
Proceedings of the IEEE Second International Conference on Smart Grid Communications, 2011

Multi-objective optimization techniques for VLSI circuits.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Robust design of power-efficient VLSI circuits.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Charge migration efficiency optimization in hybrid electrical energy storage (HEES) systems.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Versatile high-fidelity photovoltaic module emulation system.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Maximizing Profit in Cloud Computing System via Resource Allocation.
Proceedings of the 31st IEEE International Conference on Distributed Computing Systems Workshops (ICDCS 2011 Workshops), 2011

Balanced reconfiguration of storage banks in a hybrid electrical energy storage system.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Battery-supercapacitor hybrid system for high-rate pulsed load applications.
Proceedings of the Design, Automation and Test in Europe, 2011

Timing variation-aware custom instruction extension technique.
Proceedings of the Design, Automation and Test in Europe, 2011

Variation aware dynamic power management for chip multiprocessor architectures.
Proceedings of the Design, Automation and Test in Europe, 2011

Deriving a near-optimal power management policy using model-free reinforcement learning and Bayesian classification.
Proceedings of the 48th Design Automation Conference, 2011

Dynamic voltage scaling of OLED displays.
Proceedings of the 48th Design Automation Conference, 2011

Post sign-off leakage power optimization.
Proceedings of the 48th Design Automation Conference, 2011

Multi-dimensional SLA-Based Resource Allocation for Multi-tier Cloud Computing Systems.
Proceedings of the IEEE International Conference on Cloud Computing, 2011

2010
Supervised Learning Based Power Management for Multicore Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

A Markovian Decision-Based Approach for Extending the Lifetime of a Network of Battery-Powered Mobile Devices by Remote Processing.
J. Low Power Electronics, 2010

A power-optimized low-energy elliptic-curve crypto-processor.
IEICE Electronic Express, 2010

Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Multi-corner, energy-delay optimized, NBTI-aware flip-flop design.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Hybrid electrical energy storage systems.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Maximum power transfer tracking for a photovoltaic-supercapacitor energy system.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Minimizing energy consumption of a chip multiprocessor through simultaneous core consolidation and DVFS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Analysis and optimization of sequential circuit element to combat single-event timing upsets.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Power and Performance Modeling in a Virtualized Server System.
Proceedings of the 39th International Conference on Parallel Processing, 2010

Temperature-aware dynamic resource provisioning in a power-optimized datacenter.
Proceedings of the Design, Automation and Test in Europe, 2010

Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition times.
Proceedings of the Design, Automation and Test in Europe, 2010

Efficient representation, stratification, and compression of variational CSM library waveforms using Robust Principle Component Analysis.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Design and Analysis of Two Low-Power SRAM Cell Structures.
IEEE Trans. VLSI Syst., 2009

BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture.
IEEE Trans. VLSI Syst., 2009

Uncertainty-Aware Dynamic Power Management in Partially Observable Domains.
IEEE Trans. VLSI Syst., 2009

Predictive-Flow-Queue-Based Energy Optimization for Gigabit Ethernet Controllers.
IEEE Trans. VLSI Syst., 2009

Optimal Design of the Power-Delivery Network for Multiple Voltage-Island System-on-Chips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips.
J. Low Power Electronics, 2009

A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution.
J. Low Power Electronics, 2009

Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Design and application of multimodal power gating structures.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Minimizing data center cooling and server power costs.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors.
Proceedings of the 27th International Conference on Computer Design, 2009

Green computing: reducing energy cost and carbon footprint of information processing systems.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Efficient compression and handling of current source model library waveforms.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
GOP-Level Dynamic Thermal Management in MPEG-2 Decoding.
IEEE Trans. VLSI Syst., 2008

Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology.
IEEE Trans. VLSI Syst., 2008

Editorial.
ACM Trans. Design Autom. Electr. Syst., 2008

Wavelet-based dynamic power management for nonstationary service requests.
ACM Trans. Design Autom. Electr. Syst., 2008

Charge Recycling in Power-Gated CMOS Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Energy-Aware Task Scheduling and Dynamic Voltage Scaling in a Real-Time System.
J. Low Power Electronics, 2008

Heterogeneous modulation for trading-off energy balancing with bandwidth efficiency in hierarchical sensor networks.
Proceedings of the 9th IEEE International Symposium on a World of Wireless, 2008

High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Modulation-aware energy balancing in hierarchical wireless sensor networks.
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008

Improving the Efficiency of Power Management Techniques by Using Bayesian Classification.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Probabilistic error propagation in logic circuits using the Boolean difference calculus.
Proceedings of the 26th International Conference on Computer Design, 2008

Characterization and design of sequential circuit elements to combat soft error.
Proceedings of the 26th International Conference on Computer Design, 2008

Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

In-order pulsed charge recycling in off-chip data buses.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Statistical timing analysis of flip-flops considering codependent setup and hold times.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

NBTI-aware flip-flop characterization and design.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting.
Proceedings of the Design, Automation and Test in Europe, 2008

Resilient Dynamic Power Management under Uncertainty.
Proceedings of the Design, Automation and Test in Europe, 2008

A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect.
Proceedings of the Design, Automation and Test in Europe, 2008

Stochastic modeling of a thermally-managed multi-core system.
Proceedings of the 45th Design Automation Conference, 2008

A stochastic local hot spot alerting technique.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design.
IEEE Trans. VLSI Syst., 2007

Introduction to special issue on demonstrable software systems and hardware platforms.
ACM Trans. Design Autom. Electr. Syst., 2007

A Synthesis Approach for Coarse-Grained Antifuse-Based FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Parameterized Non-Gaussian Variational Gate Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Fast INC-XOR codec for low-power address buses.
IET Computers & Digital Techniques, 2007

Architectures for Silicon Nanoelectronics and Beyond.
IEEE Computer, 2007

A Unified Framework for System-Level Design: Modeling and Performance Optimization of Scalable Networking Systems.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Minimizing power dissipation during write operation to register files.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Power optimal MTCMOS repeater insertion for global buses.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Design of an efficient power delivery network in an soc to enable dynamic power management.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Sizing and placement of charge recycling transistors in MTCMOS circuits.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Active bank switching for temperature control of the register file in a microprocessor.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Sleep transistor distribution in row-based MTCMOS designs.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Dynamic power management under uncertain information.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Optimal Selection of Voltage Regulator Modules in a Power Delivery Network.
Proceedings of the 44th Design Automation Conference, 2007

Flow-Through-Queue based Power Management for Gigabit Ethernet Controller.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries.
IEEE Trans. VLSI Syst., 2006

HVS-Aware Dynamic Backlight Scaling in TFT-LCDs.
IEEE Trans. VLSI Syst., 2006

Fast Interconnect and Gate Timing Analysis for Performance Optimization.
IEEE Trans. VLSI Syst., 2006

Introduction to special issue: Novel paradigms in system-level design.
ACM Trans. Design Autom. Electr. Syst., 2006

Model-order reduction using variational balanced truncation with spectral shaping.
IEEE Trans. on Circuits and Systems, 2006

Battery-aware power management based on Markovian decision processes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Cycle-Based Decomposition of Markov Chains With Applications to Low-Power Synthesis and Sequence Compaction for Finite State Machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods.
Proceedings of the IEEE, 2006

Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Low-leakage SRAM Design with Dual V_t Transistors.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Dynamic thermal management for MPEG-2 decoding.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Low-power fanout optimization using MTCMOS and multi-Vt techniques.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Dynamic voltage and frequency management based on variable update intervals for frequency setting.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Crosstalk analysis in nanometer technologies.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

SACI: statistical static timing analysis of coupled interconnects.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Determining the optimal timeout values for a power-managed system based on the theory of Markovian processes: offline and online algorithms.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

STAX: statistical crosstalk target set compaction.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Cell delay analysis based on rate-of-current change.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Low-power design tools: are EDA vendors taking this matter seriously?
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Analysis and synthesis of quantum circuits by using quantum decision diagrams.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Non-gaussian statistical interconnect timing analysis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Charge recycling in MTCMOS circuits: concept and analysis.
Proceedings of the 43rd Design Automation Conference, 2006

Backlight dimming in power-aware mobile displays.
Proceedings of the 43rd Design Automation Conference, 2006

Statistical logic cell delay analysis using a current-based model.
Proceedings of the 43rd Design Automation Conference, 2006

B2Sim: : a fast micro-architecture simulator based on basic block characterization.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

CGTA: current gain-based timing analysis for logic cells.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Timing-driven placement based on monotone cell ordering constraints.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Parameterized block-based non-gaussian statistical gate timing analysis.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Capacitive coupling noise in high-speed VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A Leakage-aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect.
J. Low Power Electronics, 2005

Energy-Aware MPEG-4 FGS Streaming.
J. Low Power Electronics, 2005

Frame-Based Dynamic Voltage and Frequency Scaling for an MPEG Player.
J. Low Power Electronics, 2005

Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits.
IEICE Transactions, 2005

Sensitivity-Based Gate Delay Propagation in Static Timing Analysis.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Hierarchical power management with application to scheduling.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Energy efficient strategies for deployment of a two-level wireless sensor network.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Low-power fanout optimization using multiple threshold voltage inverters.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

QoM and lifetime-constrained random deployment of sensor networks for minimum energy consumption.
Proceedings of the Fourth International Symposium on Information Processing in Sensor Networks, 2005

Lifetime-aware intrusion detection under safeguarding constraints.
Proceedings of the Fourth International Symposium on Information Processing in Sensor Networks, 2005

VGTA: Variation Aware Gate Timing Analysis.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

An empirical study of crosstalk in VDSM technologies.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Modeling and Propagation of Noisy Waveforms in Static Timing Analysis.
Proceedings of the 2005 Design, 2005

HEBS: Histogram Equalization for Backlight Scaling.
Proceedings of the 2005 Design, 2005

DTM: dynamic tone mapping for backlight scaling.
Proceedings of the 42nd Design Automation Conference, 2005

A new canonical form for fast boolean matching in logic synthesis and verification.
Proceedings of the 42nd Design Automation Conference, 2005

An effective power mode transition technique in MTCMOS circuits.
Proceedings of the 42nd Design Automation Conference, 2005

Clustering techniques for coarse-grained, antifuse FPGAs.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Leakage current reduction in CMOS VLSI circuits by input vector control.
IEEE Trans. VLSI Syst., 2004

Chromatic encoding: a low power encoding technique for digital visual interface.
IEEE Trans. Consumer Electronics, 2004

Power minimization in a backlit TFT-LCD display by concurrent brightness and contrast scaling.
IEEE Trans. Consumer Electronics, 2004

Interconnect energy dissipation in high-speed ULSI circuits.
IEEE Trans. on Circuits and Systems, 2004

Transition reduction in memory buses using sector-based encoding techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

A Backlight Power Management Framework for Battery-Operated Multimedia Systems.
IEEE Design & Test of Computers, 2004

Lifetime-aware multicast routing in wireless ad hoc networks.
Proceedings of the 2004 IEEE Wireless Communications and Networking Conference , 2004

Dynamic voltage and frequency scaling based on workload decomposition.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Distributed Multimedia System Design: A Holistic Perspective.
Proceedings of the 2004 Design, 2004

A Game Theoretic Approach to Low Energy Wireless Video Streaming.
Proceedings of the 2004 Design, 2004

Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times.
Proceedings of the 2004 Design, 2004

Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling.
Proceedings of the 2004 Design, 2004

Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding.
Proceedings of the 41th Design Automation Conference, 2004

A compressed frame buffer to reduce display power consumption in mobile systems.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Technology mapping and packing for coarse-grained, anti-fuse based FPGAs.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Interconnect design methods for memory design.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Gate delay calculation considering the crosstalk capacitances.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Transmittance Scaling for Reducing Power Dissipation of a Backlit TFT-LCD.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Ground bounce in digital VLSI circuits.
IEEE Trans. VLSI Syst., 2003

A fanout optimization algorithm based on the effort delay model.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Lifetime prediction routing in mobile ad hoc networks.
Proceedings of the 2003 IEEE Wireless Communications and Networking, 2003

Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Precomputation-based Guarding for Dynamic and Leakage Power Reduction.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Buffer sizing for minimum energy-delay product by using an approximating polynomial.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Energy-Aware Wireless Video Streaming.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

Extending the lifetime of a network of battery-powered mobile devices by remote processing: a markovian decision-based approach.
Proceedings of the 40th Design Automation Conference, 2003

Technology mapping for low leakage power and high speed with hot-carrier effect consideration.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Low power synthesis of finite state machines with mixed D and T flip-flops.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

BEAM: bus encoding based on instruction-set-aware memories.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Calculating the effective capacitance for the RC interconnect in VDSM technologies.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Battery-powered digital CMOS design.
IEEE Trans. VLSI Syst., 2002

Power-optimal encoding for a DRAM address bus.
IEEE Trans. VLSI Syst., 2002

Hierarchical buffered routing tree generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Architectural energy optimization by bus splitting.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Power-Aware Bus Encoding Techniques for I/O and Data Buses in an Embedded System.
Journal of Circuits, Systems, and Computers, 2002

A Class of Irredundant Encoding Techniques for Reducing Bus Power.
Journal of Circuits, Systems, and Computers, 2002

Low power DCVSL circuits employing AC power supply.
Science in China Series F: Information Sciences, 2002

Interconnect Energy Dissipation in High-Speed ULSI Circuits.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Software-Only Bus Encoding Techniques for an Embedded System.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Buffered Routing Tree Construction under Buffer Placement Blockages.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

ALBORZ: Address Level Bus Power Optimization.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Power-aware source routing protocol for mobile ad hoc networks.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Reducing transitions on memory buses using sector-based encoding technique.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1, 2.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Frame-based dynamic voltage and frequency scaling for a MPEG decoder.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Concurrent and Selective Logic Extraction with Timing Consideration.
Proceedings of the 2002 Design, 2002

EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses.
Proceedings of the 2002 Design, 2002

2001
Estimation of peak power dissipation in VLSI circuits using thelimiting distributions of extreme order statistics.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Alphabetic trees-theory and applications in layout-driven logicsynthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Stochastic modeling of a power-managed system-construction andoptimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Gated clock routing for low-power microprocessor design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Memory Bus Encoding for Low Power: A Tutorial.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Analysis and optimization of thermal issues in high-performance VLSI.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Irredundant address bus encoding for low power.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Microprocessor power analysis by labeled simulation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service.
Proceedings of the 38th Design Automation Conference, 2001

Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs.
Proceedings of the 38th Design Automation Conference, 2001

Power optimization and management in embedded systems.
Proceedings of ASP-DAC 2001, 2001

Balanced truncation with spectral shaping for RLC interconnects.
Proceedings of ASP-DAC 2001, 2001

Low power techniques for address encoding and memory allocation.
Proceedings of ASP-DAC 2001, 2001

Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points.
Proceedings of ASP-DAC 2001, 2001

2000
Theoretical bounds for switching activity analysis in finite-state machines.
IEEE Trans. VLSI Syst., 2000

Improving the efficiency of Monte Carlo power estimation [VLSI].
IEEE Trans. VLSI Syst., 2000

Stochastic sequential machine synthesis with application to constrained sequence generation.
ACM Trans. Design Autom. Electr. Syst., 2000

Fanout optimization using bipolar LT-trees.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Simultaneous gate sizing and placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Codex-dp: co-design of communicating systems using dynamicprogramming.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Electronic design automation at the turn of the century: accomplishments and vision of the future.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Low power sequential circuit design by using priority encoding and clock gating.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Power-optimal encoding for DRAM address bus (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Analysis and Optimization of Ground Bounce in Digital CMOS Circuits.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Simultaneous Gate Sizing and Fanout Optimization.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Architectural Power Optimization by Bus Splitting.
Proceedings of the 2000 Design, 2000

Dynamic power management of complex systems using generalized stochastic Petri nets.
Proceedings of the 37th Conference on Design Automation, 2000

Timing-driven placement based on partitioning with dynamic cut-net control.
Proceedings of the 37th Conference on Design Automation, 2000

Low-power design of sequential circuits using a quasi-synchronous derived clock.
Proceedings of ASP-DAC 2000, 2000

An interleaved dual-battery power supply for battery-operated electronics.
Proceedings of ASP-DAC 2000, 2000

Analysis of power-clocked CMOS with application to the design of energy-recovery circuits.
Proceedings of ASP-DAC 2000, 2000

1999
Power Simulation and Estimation in VLSI Circuits.
Proceedings of the VLSI Handbook., 1999

Delay-optimal clustering targeting low-power VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

An integrated logical and physical design flow for deep submicron circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Interconnection analysis for standard cell layouts.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Sequence compaction for power estimation: theory and practice.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Bounded algebra and current-mode digital circuits.
J. Comput. Sci. Technol., 1999

Gate sizing with controlled displacement.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Stochastic modeling of a power-managed system: construction and optimization.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Non-stationary effects in trace-driven power analysis.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Concurrent logic restructuring and placement for timing closure.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Codex-dp: Co-design of Communicating Systems Using Dynamic Programming.
Proceedings of the 1999 Design, 1999

MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search.
Proceedings of the 36th Conference on Design Automation, 1999

Dynamic Power Management Based on Continuous-Time Markov Decision Processes.
Proceedings of the 36th Conference on Design Automation, 1999

Design Considerations for Battery-Powered Electronics.
Proceedings of the 36th Conference on Design Automation, 1999

Model Order Reduction of Large Circuits Using Balanced Truncation.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

An Integrated Battery-Hardware Model for Portable Electronics.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Timing-Driven Bipartitioning with Replication Using Iterative Quadratic Programming.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Cycle-accurate macro-models for RT-level power analysis.
IEEE Trans. VLSI Syst., 1998

Low-power state assignment targeting two- and multilevel logic implementations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Probabilistic modeling of dependencies during switching activity analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

High-level power modeling, estimation, and optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Microprocessor power estimation using profile-driven program synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Stratified random sampling for power estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Gate-level power estimation using tagged probabilistic simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Accurate and efficient power simulation strategy by compacting the input vector set.
Integr., 1998

Calculation of ramp response of lossy transmission lines using two-port network functions.
Proceedings of the 1998 International Symposium on Physical Design, 1998

Improving sampling efficiency for system level power estimation.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

A simultaneous routing tree construction and fanout optimization algorithm.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Fanout optimization under a submicron transistor-level delay model.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Gated Clock Routing Minimizing the Switched Capacitance.
Proceedings of the 1998 Design, 1998

Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation.
Proceedings of the 1998 Design, 1998

A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together.
Proceedings of the 35th Conference on Design Automation, 1998

Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics.
Proceedings of the 35th Conference on Design Automation, 1998

Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce.
Proceedings of the 35th Conference on Design Automation, 1998

A New Design for Double Edge Triggered Flip-flops.
Proceedings of the ASP-DAC '98, 1998

Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions (Embedded Tutorial).
Proceedings of the ASP-DAC '98, 1998

Power Reduction in Microprocessor Chips by Gated Clock Routing.
Proceedings of the ASP-DAC '98, 1998

An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits.
Proceedings of the ASP-DAC '98, 1998

1997
Power Optimization in VLSI Layout: A Survey.
VLSI Signal Processing, 1997

Energy minimization using multiple supply voltages.
IEEE Trans. VLSI Syst., 1997

Constructing minimal spanning/Steiner trees with bounded path length.
Integr., 1997

State assignment based on two-dimensional placement and hypercube mapping.
Integr., 1997

Factored Edge-Valued Binary Decision Diagrams.
Formal Methods in System Design, 1997

Design of Ternary CCD Circuits Referencing to Current-Mode CMOS Circuits.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Composite sequence compaction for finite-state machines using block entropy and high-order Markov models.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Post Layout Speed-up by Event Elimination.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Comparison between nMos Pass Transistor logic style vs. CMOS Complementary Cells.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

An exact solution to simultaneous technology mapping and linear placement problem.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

A Power Estimation Framework for Designing Low Power Portable Video Applications.
Proceedings of the 34st Conference on Design Automation, 1997

Hierarchical Sequence Compaction for Power Estimation.
Proceedings of the 34st Conference on Design Automation, 1997

Sequence Compaction for Probabilistic Analysis of Finite-State Machines.
Proceedings of the 34st Conference on Design Automation, 1997

Profile-Driven Program Synthesis for Evaluation of System Power Dissipation.
Proceedings of the 34st Conference on Design Automation, 1997

Statistical Estimation of the Cumulative Distribution Function for Power Dissipation in VLSI Cirucits.
Proceedings of the 34st Conference on Design Automation, 1997

A note on the relationship between signal probability and switching activity.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

Statistical design of macro-models for RT-level power evaluation.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

A new description of CMOS circuits at switch-level.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

Adaptive models for input data compaction for power simulators.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].
IEEE Trans. VLSI Syst., 1996

Power minimization in IC design: principles and applications.
ACM Trans. Design Autom. Electr. Syst., 1996

Correction to "An Approach for Multilevel Logic Optimization Targeting Low Power".
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Information theoretic measures for power analysis [logic design].
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

OBDD-based function decomposition: algorithms and implementation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

An approach for multilevel logic optimization targeting low power.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Formal Verification Using Edge-Valued Binary Decision Diagrams.
IEEE Trans. Computers, 1996

Statistical sampling and regression analysis for RT-level power evaluation.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Module assignment for low power.
Proceedings of the conference on European design automation, 1996

FPGA synthesis for minimum area, delay and power.
Proceedings of the 1996 European Design and Test Conference, 1996

Improving the Efficiency of Power Simulators by Input Vector Compaction.
Proceedings of the 33st Conference on Design Automation, 1996

Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming.
Proceedings of the 33st Conference on Design Automation, 1996

Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation.
Proceedings of the 33st Conference on Design Automation, 1996

POSE: Power Optimization and Synthesis Environment.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Power estimation methods for sequential logic circuits.
IEEE Trans. VLSI Syst., 1995

Computing the area versus delay trade-off curves in technology mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Information theoretic measures of energy consumption at register transfer level.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

PLATO P: PLA Timing Optimization by Partitioning.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Logic extraction based on normalized netlengths.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Delay optimal partitioning targeting low power VLSI circuits.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Two-level logic minimization for low power.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Minimizing the Routing Cost During Logic Extraction.
Proceedings of the 32st Conference on Design Automation, 1995

Efficient Power Estimation for Highly Correlated Input Streams.
Proceedings of the 32st Conference on Design Automation, 1995

A Fast State Assignment Procedure for Large FSMs.
Proceedings of the 32st Conference on Design Automation, 1995

Logic Extraction and Factorization for Low Power.
Proceedings of the 32st Conference on Design Automation, 1995

Register Allocation and Binding for Low Power.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Power efficient technology decomposition and mapping under an extended power consumption model.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Design and analysis of segmented routing channels for row-based FPGA's.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Control Strategies for Chip-Based DFT/BIST Hardware.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

FPGA Synthesis Using Function Decomposition.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Low power state assignment targeting two-and multi-level logic implementations.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Switching activity analysis considering spatiotemporal correlations.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Multi-level network optimization for low power.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs.
Proceedings of the 31st Conference on Design Automation, 1994

Technology Mapping Using Fuzzy Logic.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Efficient estimation of dynamic power consumption under a real delay model.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Architecture and routability analysis for row-based FPGAs.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Merging multiple FSM controllers for DFT/BIST hardware.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

FGILP: an integer linear program solver based on function graphs.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

PCUBE: A performance driven placement algorithm for low power designs.
Proceedings of the European Design Automation Conference 1993, 1993

Routability-Driven Fanout Optimization.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Technology Decomposition and Mapping Targeting Low Power Dissipation.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Minimal area merger of finite state machine controllers.
Proceedings of the conference on European design automation, 1992

A Near Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints.
Proceedings of the 29th Design Automation Conference, 1992

1991
A Flow-Oriented Approach to the Placement of Boolean Networks.
Proceedings of the VLSI 91, 1991

I/O Pad Assignment Based on the Circuit Structure.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Layout Driven Logic Restructuring/Decomposition.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Layout Driven Technology Mapping.
Proceedings of the 28th Design Automation Conference, 1991

1990
A hierarchical floorplanning approach.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Floorplanning with Pin Assignment.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
Interconnection length estimation for optimized standard cell layouts.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Automatic Layout of Silicon-on-Silicon Hybrid Packages.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Hierarchical placement for macrocells: a 'meet in the middle' approach.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988


  Loading...