Shaahin Hessabi

According to our database1, Shaahin Hessabi authored at least 88 papers between 1995 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2022
TherMa-MiCs: Thermal-Aware Scheduling for Fault-Tolerant Mixed-Criticality Systems.
IEEE Trans. Parallel Distributed Syst., 2022

Tolerating Permanent Faults With Low-Energy Overhead in Multicore Mixed-Criticality Systems.
IEEE Trans. Emerg. Top. Comput., 2022

A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues.
IEEE Access, 2022

Chapter Nine - Power-gating in NoCs.
Adv. Comput., 2022

2021
Enhancing Reliability of Emerging Memory Technology for Machine Learning Accelerators.
IEEE Trans. Emerg. Top. Comput., 2021

REALISM: Reliability-aware energy management in multi-level mixed-criticality systems with service level degradation.
J. Syst. Archit., 2021

2020
LESS-MICS: A Low Energy Standby-Sparing Scheme for Mixed-Criticality Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators.
Comput. Electr. Eng., 2020

Aging-Aware Context Switching in Multicore Processors Based on Workload Classification.
IEEE Comput. Archit. Lett., 2020

2019
On the Scheduling of Energy-Aware Fault-Tolerant Mixed-Criticality Multicore Systems with Service Guarantee Exploration.
IEEE Trans. Parallel Distributed Syst., 2019

Toward On-chip Network Security Using Runtime Isolation Mapping.
ACM Trans. Archit. Code Optim., 2019

Low-overhead thermally resilient optical network-on-chip architecture.
Nano Commun. Networks, 2019

Partition Pruning: Parallelization-Aware Pruning for Deep Neural Networks.
CoRR, 2019

2018
DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture.
IEEE Trans. Computers, 2018

Behavioral-level hardware trust: Analysis and enhancement.
Microprocess. Microsystems, 2018

PyCM: Multiclass confusion matrix library in Python.
J. Open Source Softw., 2018

SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

2017
Topology exploration of a thermally resilient wavelength-based ONoC.
J. Parallel Distributed Comput., 2017

SMART: A Scalable Mapping And Routing Technique for Power-Gating in NoC Routers.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Heterogeneous redundancy to address performance and cost in multi-core SIMT: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016
A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard.
J. Circuits Syst. Comput., 2016

Thermal and power aware task mapping on 3D Network on Chip.
Comput. Electr. Eng., 2016

TooT: an efficient and scalable power-gating method for NoC routers.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Impact of on-chip power distribution on Temperature-Induced Faults in Optical NoCs.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

AdapNoC: A fast and flexible FPGA-based NoC simulator.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
Power-efficient prefetching on GPGPUs.
J. Supercomput., 2015

Low Energy yet Reliable Data Communication Scheme for Network-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Heuristic algorithm for periodic clock optimisation in scheduling-based latency-insensitive design.
IET Comput. Digit. Tech., 2015

Cluster-based approach for improving graphics processing unit performance by inter streaming multiprocessors locality.
IET Comput. Digit. Tech., 2015

Application-based dynamic reconfiguration in optical network-on-chip.
Comput. Electr. Eng., 2015

2014
Towards a scalable, low-power all-optical architecture for networks-on-chip.
ACM Trans. Embed. Comput. Syst., 2014

All-Optical Wavelength-Routed Architecture for a Power-Efficient Network on Chip.
IEEE Trans. Computers, 2014

QuT: A low-power optical Network-on-Chip.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

2013
Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip.
Int. J. Adapt. Resilient Auton. Syst., 2013

Temperature control in three-network on chips using task migration.
IET Comput. Digit. Tech., 2013

2012
Power-efficient deterministic and adaptive routing in torus networks-on-chip.
Microprocess. Microsystems, 2012

Scalable architecture for a contention-free optical network on-chip.
J. Parallel Distributed Comput., 2012

Throughput enhancement for repetitive internal cores in latency-insensitive systems.
IET Comput. Digit. Tech., 2012

ONC3: All-Optical NoC Based on Cube-Connected Cycles with Quasi-DOR Algorithm.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses.
Microprocess. Microsystems, 2011

Hierarchical opto-electrical on-chip network for future multiprocessor architectures.
J. Syst. Archit., 2011

All-optical wavelength-routed NoC based on a novel hierarchical topology.
Proceedings of the NOCS 2011, 2011

Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Efficient periodic clock calculus in latency-insensitive design.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A Low Cost circuit level fault detection technique to Full Adder design.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

An Optical Wavelength Switching Architecture for a High-Performance Low-Power Photonic NoC.
Proceedings of the 25th IEEE International Conference on Advanced Information Networking and Applications Workshops, 2011

2010
Hierarchical on-Chip Routing of Optical Packets in Large Scale MPSoCs.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Contention-free on-chip routing of optical packets.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Low Power Encoding in NoCs Based on Coupling Transition Avoidance.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model.
Microprocess. Microsystems, 2008

A Framework for Object-Oriented Embedded System Development Based on OO-ASIPs.
J. Circuits Syst. Comput., 2008

High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A Markovian Performance Model for Networks-on-Chip.
Proceedings of the 16th Euromicro International Conference on Parallel, 2008

Energy analysis of re-injection based deadlock recovery routing algorithms.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Timing verification of distributed network systems at higher levels of abstraction.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Caspian: A Tunable Performance Model for Multi-core Systems.
Proceedings of the Euro-Par 2008, 2008

Integration of System-Level IP Cores in Object-Oriented Design Methodologies.
Proceedings of the Advances in Computer Science and Engineering, 2008

A Novel Partitioned Encoding Scheme for Reducing Total Power Consumption of Parallel Bus.
Proceedings of the Advances in Computer Science and Engineering, 2008

System-Level Assertion-Based Performance Verification for Embedded Systems.
Proceedings of the Advances in Computer Science and Engineering, 2008

Polymorphism-Aware Common Bus in an Object-Oriented ASIP.
Proceedings of the Advances in Computer Science and Engineering, 2008

PERMAP: A performance-aware mapping for application-specific SoCs.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

An Adaptive Approach to Manage the Number of Virtual Channels.
Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008

2007
Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems.
J. Comput. Syst. Sci., 2007

DotGrid: a .NET-based cross-platform software for desktop grids.
Int. J. Web Grid Serv., 2007

An assertion-based verification methodology for system-level design.
Comput. Electr. Eng., 2007

GABIST: A New Methodology to Find near Optimal LFSR for BIST Structure.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

DotGrid: A .NET-based Infrastructure for Global Grid Computing.
Proceedings of the Sixth IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2006), 2006

A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

On the Hardware-Software Partitioning: The Classic General Model (CGM).
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005
An Accurate Fir Approximation of Ideal Fractional Delay Filter with Complex Coefficients in Hilbert Space.
J. Circuits Syst. Comput., 2005

Design of Variable Fractional Delay Fir Filters with Csd Coefficients Using Genetic Algorithm.
J. Circuits Syst. Comput., 2005

The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models.
Proceedings of the Embedded Computer Systems: Architectures, 2005

A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems.
Proceedings of the Dependable Computing, Second Latin-American Symposium, 2005

Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
Object-Oriented Embedded System Development Based on Synthesis and Reuse of OO-ASIPs.
J. Univers. Comput. Sci., 2004

Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models.
Proceedings of the 2004 Design, 2004

A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
Design of variable fractional delay FIR filters using genetic algorithm.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Object-Oriented ASIP Design and Synthesis.
Proceedings of the Forum on specification and Design Languages, 2003

1995
Differential BiCMOS logic circuits: fault characterization and design-for-testability.
IEEE Trans. Very Large Scale Integr. Syst., 1995


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