Sreenivaas S. Muthyala

According to our database, Sreenivaas S. Muthyala authored at least 6 papers between 2012 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

Compacting output responses containing unknowns using an embedded processor.

Kamran Saleem, Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs.

Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

Reducing test time for 3D-ICs by improved utilization of test elevators.

Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Improving test compression with scan feedforward techniques.

Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the 2014 International Test Conference, 2014

2013

SOC test compression scheme using sequential linear decompressors with retained free variables.

Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012

Improving test compression by retaining non-pivot free variables in sequential linear decompressors.

Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the 2012 IEEE International Test Conference, 2012