Sriyash Caculo

According to our database, Sriyash Caculo authored at least 4 papers between 2018 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2025

Memory Access Vectors: Improving Sampling Fidelity for CPU Performance Simulations.

Sriyash Caculo, Mahesh Madhav, Jeff Baxter

CoRR, June, 2025

2020

A Novel and Efficient Hardware Accelerator Architecture for Signal Normalization.

Gibin ChackoGeorge, Abhishek Moitra, Sriyash Caculo, A. Amalin Prince, J. J. U. Buch, Surya K. Pathak

Circuits Syst. Signal Process., 2020

Characterizing the Scale-Up Performance of Microservices using TeaStore.

Sriyash Caculo, Kanishka Lahiri, Subramaniam Kalambur

Proceedings of the IEEE International Symposium on Workload Characterization, 2020

2018

Efficient Architecture for Implementation of Hermite Interpolation on FPGA.

Gibin ChackoGeorge, Abhishek Moitra, Sriyash Caculo, A. Amalin Prince

Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018