Sriyash Caculo

According to our database, Sriyash Caculo authored at least 5 papers between 2018 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

SPEC CPU: The Next Generation.

Mahesh Madhav, Allen Lee, Andres Mejia, Branden Moore, Charan Soppadandi, Chris Cambly, Christoph Müllner, Daniel Bowers, David Reiner, Denis Bakhvalov, Di Zhao, Duane Voth, Feng Xue, Frédérique Silber-Chaussumier, James Bucek, James Southern, Jiangning Liu, Jim Himer, John Henning, Kevin Smith, Kristen Yang, Kunal Kashyap, Mason Guy, Mat Colgrove, Michael Berg, Prasad Battini, Prasad Joshi, Rohit Prasad, Shayantika Bhattacharya, Sriyash Caculo, Stefan Reimbold, Sundar Iyengar, Van Smith, Zarko Todorovski

CoRR, May, 2026

2025

Memory Access Vectors: Improving Sampling Fidelity for CPU Performance Simulations.

Sriyash Caculo, Mahesh Madhav, Jeff Baxter

CoRR, June, 2025

2020

A Novel and Efficient Hardware Accelerator Architecture for Signal Normalization.

Gibin ChackoGeorge, Abhishek Moitra, Sriyash Caculo, A. Amalin Prince, J. J. U. Buch, Surya K. Pathak

Circuits Syst. Signal Process., 2020

Characterizing the Scale-Up Performance of Microservices using TeaStore.

Sriyash Caculo, Kanishka Lahiri, Subramaniam Kalambur

Proceedings of the IEEE International Symposium on Workload Characterization, 2020

2018

Efficient Architecture for Implementation of Hermite Interpolation on FPGA.

Gibin ChackoGeorge, Abhishek Moitra, Sriyash Caculo, A. Amalin Prince

Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018