Kanishka Lahiri

According to our database1, Kanishka Lahiri authored at least 40 papers between 1999 and 2019.

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Bibliography

2019
Performance Scaling of Cassandra on High-Thread Count Servers.
Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering, 2019

2017
Fast IPC estimation for performance projections using proxy suites and decision trees.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

DARTS: Performance-counter driven sampling using binary translators.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

2015
Characterizing Large Dataset GPU Compute Workloads Targeting Systems with Die-Stacked Memory.
Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

2010
Variation-Aware System-Level Power Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
Variation-Tolerant Dynamic Power Management at the System-Level.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.
Proceedings of the 44th Design Automation Conference, 2007

System-on-Chip Power Management Considering Leakage Power Variations.
Proceedings of the 44th Design Automation Conference, 2007

2006
The LOTTERYBUS on-chip communication architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Considering process variations during system-level power analysis.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Adaptive data placement in an embedded multiprocessor thread library.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Power analysis of mobile 3D graphics.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Signature-based workload estimation for mobile 3D graphics.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Battery discharge characteristics of wireless sensor nodes: an experimental analysis.
Proceedings of the Second Annual IEEE Communications Society Conference on Sensor, 2005

SOFTENIT: a methodology for boosting the software content of system-on-chip designs.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Design of high-performance system-on-chips using communication architecture tuners.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Design space exploration for optimizing on-chip communication architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Efficient power profiling for battery-driven embedded system design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Power analysis of system-level on-chip communication architectures.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Dynamic Platform Management for Configurable Platform-Based System-on-Chips.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
Communication-Based Power Management.
IEEE Des. Test Comput., 2002

Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Battery-efficient architecture for an 802.11 MAC processor.
Proceedings of the IEEE International Conference on Communications, 2002

Communication architecture based power management for battery efficient system design.
Proceedings of the 39th Design Automation Conference, 2002

Fast system-level power profiling for battery-efficient system design.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
System-level performance analysis for designing on-chipcommunication architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Battery Life Estimation of Mobile Embedded Systems.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs.
Proceedings of the 38th Design Automation Conference, 2001

2000
Performance Analysis of Systems with Multi-Channel Communication Architectures.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Efficient Exploration of the SoC Communication Architecture Design Space.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Fast performance analysis of bus-based system-on-chip communication architectures.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999


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