Stefan Tertinek
Orcid: 0000-0002-6664-9692
According to our database1,
Stefan Tertinek
authored at least 19 papers
between 2007 and 2024.
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Bibliography
2024
A Graph-Based Algorithm for Robust Sequential Localization Exploiting Multipath for Obstructed-LOS-Bias Mitigation.
IEEE Trans. Wirel. Commun., February, 2024
2023
Sensors, July, 2023
2022
Graph-based Simultaneous Localization and Bias Tracking for Robust Positioning in Obstructed LOS Situations.
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022
2021
A Message Passing based Adaptive PDA Algorithm for Robust Radio-based Localization and Tracking.
CoRR, 2021
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021
2020
A Harmonic Rejection Strategy for 25% Duty-Cycle IQ-Mixers Using Digital-to-Time Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Reliability and Threshold-Region Performance of TOA Estimators in Dense Multipath Channels.
Proceedings of the 2020 IEEE International Conference on Communications Workshops, 2020
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Novel Hybrid Polar-I/Q Modulation Method relaxing RF Phase Modulator Design Requirements.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
2016
Digitally controlled oscillator gain estimation for RF-DPLLs in 4G LTE polar transmitters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Proceedings of the European Wireless 2013, 2013
2011
Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Statistical Analysis of First-Order Bang-Bang Phase-Locked Loops Using Sign-Dependent Random-Walk Theory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2009
Combined Effect of Loop Delay and Reference Clock Jitter in First-order Digital Bang-bang Phase-locked Loops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Reconstruction of Nonuniformly Sampled Bandlimited Signals Using a Differentiator-Multiplier Cascade.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Phase jitter dynamics of first-order digital phase-locked loops with frequency-modulated input.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Reconstruction of Two-Periodic Nonuniformly Sampled Band-Limited Signals Using a Discrete-Time Differentiator and a Time-Varying Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, 2007